Digital readout integrated circuit for high dynamic range infrared imaging

2021 ◽  
Author(s):  
Thomas Poonnen ◽  
Sean McCotter ◽  
Kendall Esparza ◽  
Kenton Veeder
Keyword(s):  
Integrated Circuit ◽  
Infrared Imaging ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Digital Readout ◽  
Readout Integrated Circuit ◽  
High Dynamic

ACP-OPLL photonic integrated circuit for high dynamic range RF/photonic links

2011 ◽  
Author(s):  
Yifei Li ◽  
Ashish Bhardwaj ◽  
Larry Coldren ◽  
John Bowers ◽  
Peter Herczfeld
Keyword(s):  
Integrated Circuit ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Photonic Integrated Circuit ◽  
Rf Photonic Links ◽  
High Dynamic ◽  
Photonic Links

Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays

2010 ◽  
Vol 56 (4) ◽  
pp. 399-404
Author(s):  
Przemysław Rydygier ◽  
Władysław Dąbrowski ◽  
Tomasz Fiutowski ◽  
Piotr Wiącek
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Cmos Process ◽  
Clock Signal ◽  
Electrode Arrays ◽  
Control Logic ◽  
High Dynamic ◽  
Micro Electrode Arrays

Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode ArraysIn the paper we present the design and test results of an integrated circuit combining a sample&hold circuit and an analogue multiplexer. The circuit has been designed as a building block for a multi-channel Application Specific Integrated Circuit (ASIC) for recording signals from alive neuronal tissue using high-density micro-electrode arrays (MEAs). The design is optimised with respect to critical requirements for such applications, i.e. short sampling time, low power dissipation, good linearity and high dynamic range. Presented design comprises sample&hold circuits with class AB operational amplifier, novel shift register, which allows minimising cross-coupling of the clock signal and control logic. The circuit has been designed in 0.35μm CMOS process and has been successfully implemented in a prototype multi-channel ASIC.

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