A novel polysilicon light source and its on-chip optical interconnection structure design

2019 ◽  
Author(s):  
Hongliang Sun ◽  
Kaikai Xu ◽  
Jianming Zhao ◽  
Jun Yuan ◽  
Zhaotong Zhang ◽  
...  
Keyword(s):  
Light Source ◽  
Structure Design ◽  
Optical Interconnection ◽  
On Chip ◽  
Interconnection Structure

High-Temperature Operation of Photonic-Crystal Lasers for On-Chip Optical Interconnection

2012 ◽  
Vol E95.C (7) ◽  
pp. 1244-1251 ◽  
Author(s):  
Koji TAKEDA ◽  
Tomonari SATO ◽  
Takaaki KAKITSUKA ◽  
Akihiko SHINYA ◽  
Kengo NOZAKI ◽  
...  
Keyword(s):  
High Temperature ◽  
Photonic Crystal ◽  
Optical Interconnection ◽  
On Chip ◽  
High Temperature Operation

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Analysis of Thermal Properties of Power Multifinger HEMT Devices

2018 ◽  
Author(s):  
Aleš Chvála ◽  
Robert Szobolovszký ◽  
Jaroslav Kováč ◽  
Martin Florovič ◽  
Juraj Marek ◽  
...  
Keyword(s):  
Temperature Distribution ◽  
Thermal Management ◽  
High Electron Mobility Transistor ◽  
Structure Design ◽  
High Electron ◽  
Design And Optimization ◽  
Chip Temperature ◽  
Materials Used ◽  
On Chip ◽  
Measurement Approach

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

Monolithic III–nitride photonic circuit towards on-chip optical interconnection

2018 ◽  
Vol 11 (12) ◽  
pp. 122201 ◽  
Author(s):  
Yongjin Wang ◽  
Xin Wang ◽  
Jialei Yuan ◽  
Xumin Gao ◽  
Bingcheng Zhu
Keyword(s):  
Optical Interconnection ◽  
Photonic Circuit ◽  
On Chip

scholarly journals On-chip optical interconnection by using integrated III-V laser diode and photodetector with silicon waveguide

2010 ◽  
Vol 18 (15) ◽  
pp. 15440 ◽  
Author(s):  
Kazuya Ohira ◽  
Kentaro Kobayashi ◽  
Norio Iizuka ◽  
Haruhiko Yoshida ◽  
Mizunori Ezaki ◽  
...  
Keyword(s):  
Laser Diode ◽  
Optical Interconnection ◽  
Silicon Waveguide ◽  
On Chip
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