5G fronthauls with multicore fibers: CPRI signals performance degradation induced by intercore crosstalk

2019 ◽  
Author(s):  
João Lopes Rebola ◽  
Tiago M. F. Alves ◽  
Adolfo V. T. Cartaxo ◽  
André S. Marques
Keyword(s):  
Performance Degradation

GPS Receiver Performance Degradation in the Presence of Faded Interference

2016 ◽  
Author(s):  
Kyle D. Wesson ◽  
Swen D. Ericson ◽  
Terence L. Johnson ◽  
Karl W. Shallberg ◽  
Per K. Enge ◽  
...  
Keyword(s):  
Performance Degradation ◽  
Gps Receiver ◽  
Receiver Performance

General model to predict performance degradation in centrifugal pumps.

2016 ◽  
Author(s):  
Edgar Ofuchi ◽  
Ana Leticia Lima Santos ◽  
Thiago Sirino ◽  
Henrique Stel ◽  
Rigoberto Morales
Keyword(s):  
General Model ◽  
Performance Degradation ◽  
Centrifugal Pumps

scholarly journals Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache

2021 ◽  
Vol 18 (3) ◽  
pp. 1-22
Author(s):  
Michael Stokes ◽  
David Whalley ◽  
Soner Onder
Keyword(s):  
Energy Efficient ◽  
Data Access ◽  
Performance Degradation ◽  
Access Time ◽  
Data Cache ◽  
Energy Usage ◽  
Single Cycle ◽  
Performance Penalty

While data filter caches (DFCs) have been shown to be effective at reducing data access energy, they have not been adopted in processors due to the associated performance penalty caused by high DFC miss rates. In this article, we present a design that both decreases the DFC miss rate and completely eliminates the DFC performance penalty even for a level-one data cache (L1 DC) with a single cycle access time. First, we show that a DFC that lazily fills each word in a DFC line from an L1 DC only when the word is referenced is more energy-efficient than eagerly filling the entire DFC line. For a 512B DFC, we are able to eliminate loads of words into the DFC that are never referenced before being evicted, which occurred for about 75% of the words in 32B lines. Second, we demonstrate that a lazily word filled DFC line can effectively share and pack data words from multiple L1 DC lines to lower the DFC miss rate. For a 512B DFC, we completely avoid accessing the L1 DC for loads about 23% of the time and avoid a fully associative L1 DC access for loads 50% of the time, where the DFC only requires about 2.5% of the size of the L1 DC. Finally, we present a method that completely eliminates the DFC performance penalty by speculatively performing DFC tag checks early and only accessing DFC data when a hit is guaranteed. For a 512B DFC, we improve data access energy usage for the DTLB and L1 DC by 33% with no performance degradation.

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