High performance, low latency 3D sensor network for live full object reconstruction (Conference Presentation)

2018 ◽  
Author(s):  
Christoph Munkelt ◽  
Matthias Heinze ◽  
Tobias Zimmermann ◽  
Peter Kühmstedt
Keyword(s):  
Sensor Network ◽  
High Performance ◽  
Low Latency ◽  
Object Reconstruction

Fulcrum's FocalPoint FM4000: A Scalable, Low-Latency 10GigE Switch for High-Performance Data Centers

2009 ◽  
Author(s):  
Uri Cummings ◽  
Dan Daly ◽  
Rebecca Collins ◽  
Virat Agarwal ◽  
Fabrizio Petrini ◽  
...  
Keyword(s):  
High Performance ◽  
Data Centers ◽  
Performance Data ◽  
Low Latency

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Alireza Monemi ◽  
Chia Yee Ooi ◽  
Muhammad Nadzir Marsono
Keyword(s):  
High Performance ◽  
Clock Cycle ◽  
Network On Chip ◽  
Operating Frequency ◽  
Low Latency ◽  
Core System ◽  
Low Area ◽  
Area Overhead ◽  
Logic Cells ◽  
On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

Closed yet Open DRAM: Achieving Low Latency and High Performance in DRAM Memory Systems

2018 ◽  
Author(s):  
Lavanya Subramanian ◽  
Kaushik Vaidyanathan ◽  
Anant Nori ◽  
Sreenivas Subramoney ◽  
Tanay Karnik ◽  
...  
Keyword(s):  
High Performance ◽  
Memory Systems ◽  
Low Latency

scholarly journals Design of Mobile 4G Gateway Based on Zigbee Wireless Sensor Network

2018 ◽  
Vol 14 (11) ◽  
pp. 117
Author(s):  
Bo Qiu
Keyword(s):  
Wireless Sensor Network ◽  
Sensor Network ◽  
High Performance ◽  
Low Cost ◽  
Wireless Sensor ◽  
Long Distance ◽  
Hardware Platform ◽  
Gateway System ◽  
Zigbee Technology ◽  
Software And Hardware

To realize the design of mobile 4G gateway of ZigBee wireless sensor network (WSN), a scheme of wireless remote monitoring based on ZigBee and general packet radio service (GPRS) WSN gateway system is proposed. The scheme combines the advantages of short distance, low power consumption, low cost and long distance popular communication of ZigBee technology, and uses the system architecture of ZigBee + GPRS + Android. On this hardware platform, the transplantation of Android system and the development of related hardware device drivers are designed and implemented, so as to build the software platform of the system. Based on the software and hardware platform of the system, the related applications are designed and realized according to the function requirements of the system, and the software and hardware platform and the application program are tested and analyzed. The test results show that the system runs steadily and has good performance. To sum up, the hardware platform has the advantages of low energy consumption, high performance and scalability.

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