A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time

In light of a growing research interest in the innovation potential that lies at the intersection of design, technology, and science, this paper offers a literature review of design initiatives centered on scientific discovery and invention. The focus of this paper is on evidence of design capabilities in the academic research environment. The results are structured along the Four Orders of Design, with examples of design-in-science initiatives ranging from (1) the design of scientific figures and (2) laboratory devices using new technology to (3) interactions in design workshops for scientists and (4) interdisciplinary design labs. While design capabilities have appeared in all four orders of design, there are barriers and cultural constraints that have to be taken into account for working at or researching these creative intersections. Modes of design integration and potentially necessary adaptations of design practice are therefore also highlighted.

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A Review on Run-Time Reconfigurations and Code Update Mechanisms in Wireless Sensor Networks

International Journal of Innovative Research in Computer and Communication Engineering ◽

10.15680/ijircce.2015.0302044 ◽

2015 ◽

Vol 03 (02) ◽

pp. 1015-1032

Author(s):

Rekha.K.S., Dr.T.H.Sreenivas

Keyword(s):

Wireless Sensor Networks ◽

Sensor Networks ◽

Wireless Sensor ◽

Run Time

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Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e94.a.2597 ◽

2011 ◽

Vol E94-A (12) ◽

pp. 2597-2608 ◽

Cited By ~ 1

Author(s):

Lovic GAUTHIER ◽

Tohru ISHIHARA

Keyword(s):

Energy Consumption ◽

Time Management ◽

Data Placement ◽

Energy Consumption Reduction ◽

Scratch Pad Memory ◽

Consumption Reduction ◽

Run Time ◽

Embedded Applications

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An Approach to Assessing the Environmental Impact Tradeoffs from Design, Technology, and Flight Procedures in Airport Area Operations

9th AIAA Aviation Technology, Integration, and Operations Conference (ATIO) ◽

10.2514/6.2009-7048 ◽

2009 ◽

Author(s):

Paul Brett ◽

Michelle Kirby ◽

Dimitri Mavris

Keyword(s):

Environmental Impact ◽

Design Technology

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Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽

2009 ◽

Author(s):

Moshe Pelleh

Keyword(s):

Embedded Systems ◽

Embedded System ◽

General Purpose ◽

Experimental Results ◽

Medium Size ◽

Organic System ◽

Software Application ◽

Organic Systems ◽

Special Cases ◽

Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

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Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0771 ◽

2002 ◽

Author(s):

Hui Pan ◽

Thomas Gibson

Keyword(s):

Failure Analysis ◽

Focused Ion Beam ◽

Ion Beam ◽

Electrical Characterization ◽

Charge Pump ◽

Front Side ◽

Pump Failure ◽

Electrical Failure ◽

Optical Proximity Correction ◽

A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

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