Structure design of AlN double-ended tuning fork resonators

2017 ◽  
Author(s):  
LEI Qiang ◽  
Yang Gao ◽  
Han Chao
Keyword(s):  
Tuning Fork ◽  
Structure Design

Structure Design of a Novel Micromachinined Tuning Fork Gyroscope with High Robustness

2012 ◽  
Vol 503 ◽  
pp. 108-113
Author(s):  
W.P. Chen ◽  
Yi Bo Yang ◽  
Y. Yu
Keyword(s):  
Atmospheric Pressure ◽  
Tuning Fork ◽  
Angular Rate ◽  
Structure Design ◽  
Framework Structure ◽  
Mechanical Coupling ◽  
Vibratory Gyroscope ◽  
Air Damping ◽  
Capacitor Structure ◽  
Silicon Based

A novel silicon based dual-mass vibrating tuning fork vibratory gyroscope (TFG) with differential capacitor structure is designed in this paper. the U-shaped beam is adapted to connecting the two decoupling movement of the framework structure in order to achieve the independent of the movement of drive direction and sense direction. The TFG structure is also optimized to further reduce the mechanical coupling of the device. The drive combs are designed on the mass, while the sense combs are designed on the frame. All the combs in this gyroscope are dominated by slide-film air damping in order to lower the air damping. This gyroscope is designed to obtain robust operation against variations under atmospheric pressure condition. The TFG is tested at atmospheric pressure with a sensitivity of 17.8mV/◦/s and a linearity of 99.989%, capacitance structure sensitivity is 21.5αf/◦/s with an equivalent noise angular rate of 0.028◦/s/Hz1/2, respective.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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