Coding for parallel execution of hardware-in-the-loop millimeter-wave scene generation models on multicore SIMD processor architectures

2013 ◽  
Author(s):  
Richard F. Olson
Author(s):  
Mario Schölzel ◽  
Pawel Pawlowski ◽  
Adam Dabrowski

Statically scheduled superscalar processors (e.g. very long instruction word processors) are characterized by multiple parallel execution units and small sized control logic. This makes them easy scalable and therefore attractive for the use in embedded systems as application specific processors. The shrinking feature size in CMOS technology makes such processors in long living embedded systems more susceptible to several types of faults. Therefore, it should be possible to run an application, even if one or more components in the data path of a statically scheduled processor become permanently faulty. Then it becomes necessary either to reconfigure the hardware or to reconfigure the executed program such that operations are scheduled around the faulty units. The authors present recent investigations to reschedule operations in the field either on-line in hardware or off-line in software. Thus, the reconfiguration of the program is either done dynamically by the hardware or permanently by self-modifying code. If a permanent fault is present in the data path, then in both cases a delay may occur during the execution of the application. This graceful performance degradation may become critical for real-time applications. A framework to overcome this problem by using scalable algorithms is provided, too.


1995 ◽  
Vol 7 (1) ◽  
pp. 89-100
Author(s):  
H. C. Han ◽  
E. S. Mansueto
Keyword(s):  

Author(s):  
Brian Drouin ◽  
Rod Kim ◽  
M.-C. Chang ◽  
Alexander Raymond ◽  
Timothy Crawford ◽  
...  

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