Low-complexity image processing for a high-throughput low-latency snapshot multispectral imager with integrated tiled filters

2013 ◽  
Author(s):  
Bert Geelen ◽  
Murali Jayapala ◽  
Nicolaas Tack ◽  
Andy Lambrechts
Keyword(s):  
Image Processing ◽  
High Throughput ◽  
Low Complexity ◽  
Low Latency ◽  
Multispectral Imager

scholarly journals FPGA Implementation of Hardware Architecture for H264/AV Codec Standards

2013 ◽  
Vol 2 (01) ◽  
pp. 01-07
Author(s):  
Prof. Naveen Jain
Keyword(s):  
Wireless Networks ◽  
Discrete Cosine Transform ◽  
Video Compression ◽  
High Throughput ◽  
Low Complexity ◽  
Prediction Equation ◽  
Parallel Process ◽  
Fpga Implementation ◽  
Low Latency ◽  
Efficient Utilization

The proposed work is a modern hardware based architecture for performing transformation, quantisation and prediction is designed which is used for H.264/AVC video standards. This designed hardware find its importance in advanced H264 encoders which are repeatedly find its application in HDTV applications. The H264/AV Codec does video compression and video decompression for prospect broadband and wireless networks.  A low complexity discrete cosine transform is used by DSP embedded multiplier. An intra-prediction equation are employed to get low latency, high throughput, efficient utilization of resources. The proposed architecture also employs both pipeline & parallel process methods. The proposed architecture is implemented using VHDL and synthesised for Virtex 5, and the device is 5vlx50tff665.

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

scholarly journals A high throughput architecture for a low complexity soft-output demapping algorithm

2015 ◽  
Vol 13 ◽  
pp. 73-80 ◽  
Author(s):  
I. Ali ◽  
U. Wasenmüller ◽  
N. Wehn
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Turbo Code ◽  
Low Complexity ◽  
Implementation Cost ◽  
Qam Modulation ◽  
Iterative Systems ◽  
Very High ◽  
Complexity Algorithm ◽  
Hardware Performance

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

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