CCD/CMOS process for integrated image acquisition and early vision signal processing

1990 ◽  
Author(s):  
Craig L. Keast ◽  
Charles G. Sodini
Keyword(s):  
Signal Processing ◽  
Image Acquisition ◽  
Cmos Process ◽  
Early Vision

Low Common-Mode Gain Instrumentation Amplifier Architecture Insensitive to Resistor Mismatches

2016 ◽  
Vol 6 (6) ◽  
pp. 3247 ◽  
Author(s):  
Zainul Abidin ◽  
Koichi Tanno ◽  
Shota Mago ◽  
Hiroki Tamura
Keyword(s):  
Signal Processing ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Common Mode ◽  
Evaluation Result ◽  
Biological Signal ◽  
Common Mode Voltage ◽  
Biological Signal Processing ◽  
Differential Difference Amplifier

<pre>In this paper, an instrumentation amplifier architecture for biological <br />signal is proposed. First stage of conventional IA architecture was modified <br />by using fully balanced differential difference amplifier and evaluated by <br />using <span>1P</span> <span>2M</span> 0.6<span>μ</span>m CMOS process. From <span>HSPICE</span> simulation result, lower <br />common-mode voltage can be achieved by proposed IA architecture. <br />Actual fabrication was done and six chips were evaluated. From the evaluation result, average common-mode gain of proposed IA architecture <br />is <span>10.84</span> dB lower than that of conventional one without requiring <br />well-matched resistors. Therefore, the proposed IA architecture <br />is suitable for biological signal processing.<br /><br /></pre>

scholarly journals Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1303
Author(s):  
Hoontaek Lee ◽  
Junsoo Kim ◽  
Kumjae Shin ◽  
Wonkyu Moon
Keyword(s):  
Signal Processing ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Effect Transistor

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The - characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

Analog VLSI systems for image acquisition and fast early vision processing

1992 ◽  
Vol 8 (3) ◽  
pp. 217-230 ◽  
Author(s):  
John L. Wyatt ◽  
Craig Keast ◽  
Mark Seidel ◽  
David Standley ◽  
Berthold Horn ◽  
...  
Keyword(s):  
Image Acquisition ◽  
Analog Vlsi ◽  
Early Vision ◽  
Vision Processing

scholarly journals Implementation of a fully implantable middle-ear hearing device chip

2021 ◽  
Vol 29 ◽  
pp. 399-413
Author(s):  
Jyung Hyun Lee ◽  
Dong Wook Kim ◽  
Ki Woong Seong ◽  
Myoung Nam Kim ◽  
Jin-Ho Cho
Keyword(s):  
Signal Processing ◽  
Middle Ear ◽  
Hearing Aids ◽  
Cmos Process ◽  
Verilog Hdl ◽  
Pulse Density ◽  
Implantable Microphone ◽  
Hearing Device ◽  
Point Fast Fourier Transform ◽  
Signal Processor

BACKGROUND AND OBJECTIVE: Recently, with the increase in the population of hearing impaired people, various types of hearing aids have been rapidly developed. In particular, a fully implantable middle ear hearing device (F-IMEHD) is developed for people with sensorineural hearing loss. The F-IMEHD system comprises an implantable microphone, a transducer, and a signal processor. The signal processor should have a small size and consume less power for implantation in a human body. METHODS: In this study, we designed and fabricated a signal-processing chip using the modified FFT algorithm. This algorithm was developed focusing on eliminating time delay and system complexity in the transform process. The designed signal-processing chip comprises a 4-channel WDRC, a fitting memory, a communication 1control part, and a pulse density modulator. Each channel is separated using a 64-point fast Fourier transform (FFT) method and the gain value is matched using the fitting table in the fitting memory. RESULTS AND CONCLUSION: The chip was designed by Verilog-HDL and the designed HDL codes were verified by Modelsim-PE 10.3 (Mentor graphics, USA). The chip was fabricated using a 0.18 μm CMOS process (SMIC, China). Experiments were performed on a cadaver to verify the performance of the fabricated chip.

Low Noise and Low Distortion Telescopic OTA for Biomedical Signal Processing

2019 ◽  
Vol 12 (6) ◽  
pp. 507-512
Author(s):  
Zuber M. Patel
Keyword(s):  
Signal Processing ◽  
Negative Feedback ◽  
Flicker Noise ◽  
Low Noise ◽  
Biomedical Signal Processing ◽  
Corner Frequency ◽  
Cmos Process ◽  
Biomedical Signal ◽  
Low Distortion ◽  
Source Degeneration

Background: This paper presents a low noise and low distortion telescopic Operational Trans-conductance Amplifier (OTA) that is suited to biomedical signal processing. In our proposal, source degeneration using CMOS transmission gate is introduced in telescopic OTA to realize current- voltage negative feedback. The negative feedback degenerates Gm, reduces flicker noise and reduces distortion. Methods: The circuit is simulated by using TSMC 90nm CMOS process technology with 1.8V supply voltage. We obtained promising simulation results that show THD less than -90dB and flicker noise 60 nV at 4kHz corner frequency. Results: The frequency response plot reveals that our circuit offers a voltage gain of 63dB with negative feedback and achieves a phase margin of about 70 degrees. Thus, this topology is a feasible solution for low noise and low distortion biomedical signal amplifier circuits. Conclusion: A highly linear and low noise telescopic OTA topology was proposed in this paper. A simple but efficient technique of source degeneration is used with negative feedback to achieve low distortion and low noise.

The Application of CCD Sensor in Fabric Defect

2013 ◽  
Vol 325-326 ◽  
pp. 866-869
Author(s):  
Guo Sheng Xu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Data Model ◽  
Image Acquisition ◽  
Practical Application ◽  
Time System ◽  
Real Time System ◽  
Ccd Sensor ◽  
Fabric Defect ◽  
Defects Analysis

In order to detect the fabric defects automatically, a real-time system and algorithm for the detection were developed in which the hardware part included image acquisition, signal processing and illumination device. The ring data model of defect silhouette is constructed to subsequent defects analysis. At last, examples prove that this algorithm can accomplish extraction of fabric defect silhouette preferably. The verification indicates that the design can satisfy the requirements of practical application well and make the detection flexible and convenient.

Design of Low-Power SoC for Wearable Healthcare Device

2019 ◽  
Vol 29 (06) ◽  
pp. 2050085
Author(s):  
Ji Kwang Kim ◽  
Jung Hwan Oh ◽  
Gwan Beom Hwang ◽  
Oh Seong Gwon ◽  
Seung Eun Lee
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Wearable Devices ◽  
Computation Offloading ◽  
Cmos Process ◽  
Embedded Processor ◽  
System A ◽  
Low Power System ◽  
On Chip

In wearable devices, power consumption is a serious issue since wearable devices must maintain the power-on state at any time. In healthcare system, a variety of signal processing operations occupy a large portion of overall workload because it has periodic and heavy computational workloads. In this paper, we propose a low-power System on Chip (SoC) architecture for wearable healthcare devices. In order to reduce power consumption of processor, we design a hardware accelerator that handles signal processing and provides computation offloading. Furthermore, to minimize the area and maximize the performance of the accelerator, we optimize the operation bit-width by analyzing the frequency response. The low-power healthcare SoC was fabricated with 0.11[Formula: see text][Formula: see text]m CMOS process. Finally, we measured the power consumption of our chip and verified the applicability of the digital filter accelerator, which reduces the energy consumption for embedded processor.

A Multiplexer with Split Devices for High Channel Isolation

2014 ◽  
Vol 644-650 ◽  
pp. 3678-3681
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
Jun Luo ◽  
...  
Keyword(s):  
Signal Processing ◽  
Processing System ◽  
Analog Signal ◽  
Signal Acquisition ◽  
Cmos Process ◽  
Noise Propagation ◽  
Signal Processing System ◽  
Design Work ◽  
High Isolation ◽  
Isolation Performance

A multiplexer with split devices for high channel isolation was proposed in this paper. The multiplexer is the most essential circuitry for multi-channel video signal acquisition systems. In the multi-channel applications, high isolation performance is required basically for the efficient signal processing. The noise propagation between channels is unexpected. The split devices technique is employed in the design work. Redundant transistors are inserted between the split cells to realize the noise grounded. This multiplexer is simulated and verified in the commercial CMOS process, and the isolation of more than 70dB was achieved. It has been embedded in a multi-channel analog signal processing system.

A Low Power Amplifier for Bio-Signal Processing

2011 ◽  
Vol 108 ◽  
pp. 289-293
Author(s):  
Tao Zhou
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Power Amplifier ◽  
Low Voltage ◽  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Very Low Frequency ◽  
Voltage Amplifier

This paper presents a low voltage amplifier with low noise and very low frequency designed for bio-signal processing. The amplifier requires only ± 0.6V supply and consumes 1.24μW, with a 75.5 dB gain over a bandwidth covering a range of frequencies from some hundreds of mHz to 19 kHz. A SMIC 0.13μm CMOS process is used in design and simulation.

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