High-speed optical links between Lawrence Livermore National Lab. and Univ. of California/Berkeley

1994 ◽  
Author(s):  
W. J. Lennon ◽  
R. L. Thombley
Keyword(s):  
High Speed ◽  
Optical Links

A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

2022 ◽  
Vol 17 (01) ◽  
pp. C01040
Author(s):  
C. Zhao ◽  
D. Guo ◽  
Q. Chen ◽  
N. Fang ◽  
Y. Gan ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Test Results ◽  
Eye Diagram ◽  
Optical Links ◽  
Optical Module ◽  
Active Feedback ◽  
High Bandwidth ◽  
Output Driver ◽  
Very High

Abstract This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

High-speed optical links

2019 ◽  
Author(s):  
Azita Emami ◽  
Kuan-Chang Chen ◽  
Arian Hashemi
Keyword(s):  
High Speed ◽  
Optical Links

Reconfigurable Forward Error Correction Decoder for Beyond 100 Gbps High Speed Optical Links

2015 ◽  
Vol 19 (2) ◽  
pp. 119-122 ◽  
Author(s):  
Bomin Li ◽  
Knud J. Larsen ◽  
Darko Zibar ◽  
Idelfonso Tafur Monroy
Keyword(s):  
Error Correction ◽  
High Speed ◽  
Forward Error Correction ◽  
Optical Links ◽  
Forward Error

scholarly journals Radiation-hard/high-speed data transmission using optical links

2009 ◽  
Vol 197 (1) ◽  
pp. 175-179
Author(s):  
K.K. Gan ◽  
B. Abi ◽  
W. Fernando ◽  
H.P. Kagan ◽  
R.D. Kass ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Optical Links ◽  
High Speed Data ◽  
Radiation Hard ◽  
Speed Data Transmission

CMOS ADC-based receivers for high-speed electrical and optical links

2016 ◽  
Vol 54 (10) ◽  
pp. 168-175 ◽  
Author(s):  
Samuel Palermo ◽  
Sebastian Hoyos ◽  
Ayman Shafik ◽  
Ehsan Zhian Tabasy ◽  
Shengchang Cai ◽  
...  
Keyword(s):  
High Speed ◽  
Optical Links

DO upgrade: Central Tracking readout electronics utilizing high speed optical links

2002 ◽  
Author(s):  
M. Baert ◽  
F. Borcherding ◽  
M. Johnson ◽  
M. Martin ◽  
M. Matulik ◽  
...  
Keyword(s):  
High Speed ◽  
Readout Electronics ◽  
Optical Links

Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects

2003 ◽  
Author(s):  
Ping Gui ◽  
Fouad Kiamilev ◽  
Xiaoqing Wang ◽  
Michael McFadden ◽  
Charlie Kuznia ◽  
...  
Keyword(s):  
Free Space ◽  
High Speed ◽  
Flip Chip ◽  
Data Rate ◽  
Cavity Surface ◽  
Cmos Process ◽  
Free Space Optical ◽  
Optical Links ◽  
Parallel Optical Interconnects ◽  
Emitting Lasers

Double data rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous, DDR optical signaling. On the transmit side, two 8-bit electrical inputs are multiplexed, encoded and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-bit electrical outputs. Our IC integrates analog Vertical Cavity Surface Emitting Lasers (VCSEL), drivers and optical receivers with digital DDR multiplexing, serialization, and deserializaton circuits. It was fabricated in a 0.5-micron Silicon-on-Sapphire (SOS) CMOS process. Linear arrays of quad VCSELs and photodetectors were attached to our transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mbps with a 250 MHz DDR clock, achieving a gigabit of aggregate bandwidth. While our DDR scheme is well suited for low-skew fiber-ribbon, free-space and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To our knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.

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