10-Gbytes/s, three-dimensional parallel optical interconnects using a novel conductive polymer flip-chip process

2004 ◽  
Vol 43 (11) ◽  
pp. 2511
Author(s):  
Saurabh K. Lohokare
Keyword(s):  
Optical Interconnects ◽  
Flip Chip ◽  
Conductive Polymer ◽  
Three Dimensional ◽  
Parallel Optical Interconnects

Low-crosstalk 10-Gb/s flip-chip array module for parallel optical interconnects

2005 ◽  
Vol 17 (7) ◽  
pp. 1516-1518 ◽  
Author(s):  
Sang Hyun Park ◽  
Sung Min Park ◽  
Hyo-Hoon Park ◽  
Chul Soon Park
Keyword(s):  
Optical Interconnects ◽  
Flip Chip ◽  
Parallel Optical Interconnects

64-channel flip-chip-mounted selectively oxidized GaAs VCSEL array for parallel optical interconnects

1999 ◽  
Author(s):  
Christian Jung ◽  
Roger King ◽  
Roland Jaeger ◽  
Martin Grabherr ◽  
Franz Eberhard ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
Flip Chip ◽  
Parallel Optical Interconnects

1K channel optical interconnects of CMOS-PQR flip chip

2004 ◽  
Author(s):  
O'Dae Kwon ◽  
Kwonsub Lim ◽  
Jungyoun Kim ◽  
Sangkyeom Kim ◽  
Moojin Kim ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
Flip Chip

Three-dimensional polymer mode (de)multiplexer with cascaded tapered couplers for on-board optical interconnects

2021 ◽  
Author(s):  
Yuling Shang ◽  
Wenjie Guo ◽  
Xiang He ◽  
Jinzhuo Zhou ◽  
Yaya Yan ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
Three Dimensional

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

2011 ◽  
Author(s):  
Kohta Nakahira ◽  
Hironori Tago ◽  
Fumiaki Endo ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Thermal Deformation ◽  
Flip Chip ◽  
Flexural Rigidity ◽  
Three Dimensional ◽  
Strain Gauges ◽  
Copper Interconnection ◽  
Induced Stress ◽  
Alignment Structure

Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.

Finite Element Analysis of Stress Singularities in Attached Flip Chip Packages

2000 ◽  
Vol 122 (4) ◽  
pp. 301-305 ◽  
Author(s):  
A. Q. Xu ◽  
H. F. Nied
Keyword(s):  
Contact Angle ◽  
Finite Element ◽  
Glass Fiber ◽  
Flip Chip ◽  
Three Dimensional ◽  
Stress Singularity ◽  
Local Stress ◽  
Stress Singularities ◽  
Element Analysis ◽  
Three Dimensional Finite Element

Cracking and delamination at the interfaces of different materials in plastic IC packages is a well-known failure mechanism. The investigation of local stress behavior, including characterization of stress singularities, is an important problem in predicting and preventing crack initiation and propagation. In this study, a three-dimensional finite element procedure is used to compute the strength of stress singularities at various three-dimensional corners in a typical Flip-Chip assembled Chip-on-Board (FCOB) package. It is found that the stress singularities at the three-dimensional corners are always more severe than those at the corresponding two-dimensional edges, which suggests that they are more likely to be the potential delamination sites. Furthermore, it is demonstrated that the stress singularity at the upper silicon die/epoxy fillet edge can be completely eliminated by an appropriate choice in geometry. A weak stress singularity at the FR4 board/epoxy edge is shown to exist, with a stronger singularity located at the internal die/epoxy corner. The influence of the epoxy contact angle and the FR4 glass fiber orientation on stress state is also investigated. A general result is that the strength of the stress singularity increases with increased epoxy contact angle. In addition, it is shown that the stress singularity effect can be minimized by choosing an appropriate orientation between the glass fiber in the FR4 board and the silicon die. Based on these results, several guidelines for minimizing edge stresses in IC packages are presented. [S1043-7398(00)00904-X]

1‐to‐12 surface normal three‐dimensional optical interconnects

1993 ◽  
Vol 63 (14) ◽  
pp. 1883-1885 ◽  
Author(s):  
Ray T. Chen ◽  
Suning Tang ◽  
Maggie M. Li ◽  
David Gerald ◽  
Srikanth Natarajan
Keyword(s):  
Optical Interconnects ◽  
Three Dimensional ◽  
Surface Normal
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