Empirical implantation damage model and its effect on reverse short channel effect for 0.35 μm complementary metal–oxide–semiconductor technology

1998 ◽  
Vol 16 (1) ◽  
pp. 430
Author(s):  
Jongmin Kim
Keyword(s):  
Metal Oxide ◽  
Damage Model ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Technology ◽  
Short Channel ◽  
Short Channel Effect ◽  
Implantation Damage ◽  
Channel Effect

The Choice of MOSFET Manufacturing Technique Used in Emergency Response Robot

2020 ◽  
Author(s):  
Liu Yining ◽  
Wang Renze ◽  
Yang Yapeng ◽  
Zhang Jiangang ◽  
Wang Ning ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Radiation Effects ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Short Channel ◽  
Threshold Voltage Shift ◽  
Channel Effect ◽  
Radiation Induced

Abstract For the aim of helping the development of robots used in Radiological Emergency Planning and Preparedness, the Total Ionizing Dose (TID) effects on the threshold voltage shift (ΔVth) of different kinds of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with different geometry and different scaling technology was compared. The different gate width and length dependent between bulk Complementary Metal-Oxide-Semiconductor Transistor (CMOS) process and nanowire (NW) MOSFET as well as higher and lower technology node is noticed. The reason of this difference is explained from the aspects of Radiation Induced Narrow channel effect (RINCE) and Radiation Induced Short channel effect (RISCE). It is found that some studies in recent years have corrected the influence of negative bias temperature instability (NBTI) when considering radiation effects. The TID effects on ΔVth of several kinds of new devices such as MOSFETs with new layout geometry as well as Ge-channel and GaN channel MOSFETs are described which can be investigated more deeply.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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