Surface Fermi level engineering: Or there is more to Schottky barriers than just making diodes and field effect transistor gates

1991 ◽  
Vol 9 (4) ◽  
pp. 2355 ◽  
Author(s):  
J. L. Freeouf
Keyword(s):  
Fermi Level ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Schottky Barriers ◽  
Effect Transistor ◽  
Surface Fermi Level

Schottky Barrier 3C-SiC Nanowire Field Effect Transistor

2011 ◽  
Vol 679-680 ◽  
pp. 613-616 ◽  
Author(s):  
Konstantinos Rogdakis ◽  
Edwige Bano ◽  
Laurent Montes ◽  
Mikhael Bechelany ◽  
David Cornu ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Schottky Contact ◽  
Schottky Barriers ◽  
Catalyst Free ◽  
Effect Transistor ◽  
Contact Barrier ◽  
Gating Effect

Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowire (NW) were fabricated. Devices with rectifying Source (S) and Drain (D) contacts have been observed. In contrast with the ohmic-like devices reported in the literature, the Schottky contact barrier (SB) at S/ D regions acts beneficially for the FET performance by suppressing the off-current. At high positive gate voltages (>10 V), the Schottky barriers tend to be more transparent leading to ION/IOFF ratio equal to ~ 103 in contrast to the weak gating effect of the ohmic-contacted 3C-SiC NWFETs.

Imaging Schottky Barriers at Carbon Nanotube Contacts

2001 ◽  
Vol 706 ◽  
Author(s):  
Marcus Freitag ◽  
A. T. Johnson
Keyword(s):  
Carbon Nanotube ◽  
Schottky Barrier ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Schottky Barriers ◽  
Scanning Gate Microscopy ◽  
Gating Mechanism ◽  
Effect Transistor ◽  
Semiconducting Nanotubes

AbstractWe use scanning gate microscopy to precisely locate the gating response in single-wall nanotube devices. Junctions of metallic and semiconducting nanotubes show a dramatic increase in transport current when they are electrostatically doped with holes at the junction. We ascribe this behavior to the turn-on of a reverse biased Schottky barrier. A similar effect is seen in field-effect transistors made from an individual semiconducting single-wall carbon nanotube. In this case, there are two Schottky barriers at the metal contacts, one of which is forward, and one of which is reverse biased. The gating action is only observed at the reverse biased Schottky barrier at the positive electrode. By positioning the gate near one of the contacts, we convert the nanotube field-effect transistor into a rectifying nanotube diode. These experiments both clarify the gating mechanism for nanotube devices and indicate a strategy for diode fabrication based on controlled placement of acceptor impurities at a nanotube field-effect transistor.

scholarly journals GaAs Microcircuit Contact and Interconnect Technology

1982 ◽  
Vol 18 ◽  
Author(s):  
Bryant .M Welch
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistor ◽  
Schottky Barriers ◽  
Current Status ◽  
High Yield ◽  
Effect Transistor ◽  
And Performance ◽  
Interconnect Technology

The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance.The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature.The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer

2010 ◽  
Vol E93-C (5) ◽  
pp. 540-545 ◽  
Author(s):  
Dong Seup LEE ◽  
Hong-Seon YANG ◽  
Kwon-Chil KANG ◽  
Joung-Eob LEE ◽  
Jung Han LEE ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor

Biosensor Based on Ion-Sensitive Field-Effect Transistor Using Minimum Contact to Float-ing Gate

2019 ◽  
Vol 24 (4) ◽  
pp. 407-414
Author(s):  
Oksana V. Gubanova ◽  
◽  
Evgeniy V. Kuznetsov ◽  
Elena N. Rybachek ◽  
Alexander N. Saurov ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor
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