Testing integrated circuit microstructures using charging-induced voltage contrast

1990 ◽  
Vol 8 (6) ◽  
pp. 2041 ◽  
Author(s):  
T. J. Aton
Keyword(s):  
Integrated Circuit ◽  
Induced Voltage ◽  
Voltage Contrast

Circuit Tracing on Integrated Circuit Using FIB Passive Voltage Contrast Effect

2015 ◽  
Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer ◽  
Michael W. Phaneuf
Keyword(s):  
Electron Microscope ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Database System ◽  
Conventional Procedure ◽  
Sem Imaging ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Graphic Database

Abstract Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

scholarly journals Direct Charge Measurement in Floating Gate Transistors of Flash EEPROM Using Scanning Electron Microscopy

2016 ◽  
Author(s):  
Franck Courbon ◽  
Sergei Skorobogatov ◽  
Christopher Woods
Keyword(s):  
Scanning Probe Microscopy ◽  
Integrated Circuit ◽  
Memory Cell ◽  
Processing Technique ◽  
Floating Gate ◽  
Scanning Probe ◽  
Image Processing Technique ◽  
Data Retention ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract We present a characterization methodology for fast direct measurement of the charge accumulated on Floating Gate (FG) transistors of Flash EEPROM cells. Using a Scanning Electron Microscope (SEM) in Passive Voltage Contrast (PVC) mode we were able to distinguish between '0' and '1' bit values stored in each memory cell. Moreover, it was possible to characterize the remaining charge on the FG; thus making this technique valuable for Failure Analysis applications for data retention measurements in Flash EEPROM. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Only a relatively simple backside sample preparation is necessary for accessing the FG of memory transistors. The technique presented was successfully implemented on a 0.35 μm technology node microcontroller and a 0.21 μm smart card integrated circuit. We also show the ease of such technique to cover all cells of a memory (using intrinsic features of SEM) and to automate memory cells characterization using standard image processing technique.

Techniques for Localization of IC Interconnection Defects

2002 ◽  
Vol 716 ◽  
Author(s):  
Edward I. Cole
Keyword(s):  
Integrated Circuit ◽  
Constant Current ◽  
Induced Voltage ◽  
Contrast Imaging ◽  
Thermally Induced ◽  
Imaging Results ◽  
Starting Point ◽  
Site Localization ◽  
Scanning Optical Microscopy ◽  
Failure Site

AbstractThe advances in integrated circuit technology has made failure site localization extremely challenging. Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Light-Induced Voltage Alteration (LIVA), Seebeck Effect Imaging (SEI) and Thermally-Induced Voltage Alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy (SEM) techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects. In addition to the techniques listed above, the Resistive Contrast Imaging (RCI) for localizing opens on metal test patterns will be described as a starting point for the “IVA” technologies.

Failure Analysis of FinFET Circuitry at GHz Speeds Using Voltage-Contrast and Stroboscopic Techniques on a Scanning Electron Microscope

2019 ◽  
Author(s):  
James Vickers ◽  
Seema Somani ◽  
Blake Freeman ◽  
Pete Carleson ◽  
Lubomír Tùma ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Electrical Activity ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Contrast Mechanism ◽  
Voltage Contrast ◽  
Working Device ◽  
Scanning Electron

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Scanning Optical Microscopy Application in Micron® Memory Devices

2005 ◽  
Author(s):  
Wong Yaw Yuan ◽  
T.L. Edmund Poh ◽  
David Lam
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Memory Devices ◽  
Back Side ◽  
Induced Voltage ◽  
Scanning Optical Microscopy ◽  
Side Emission ◽  
Complex Circuits

Abstract The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.

Electron-beam-induced voltage contrast and modulated optical reflectance studies of YBCO thin film resonators

1998 ◽  
Vol 11 (4) ◽  
pp. 378-382 ◽  
Author(s):  
S A L Foulds ◽  
D P Almond ◽  
P Nokrach ◽  
F Wellhöfer ◽  
P Woodall ◽  
...  
Keyword(s):  
Thin Film ◽  
Electron Beam ◽  
Induced Voltage ◽  
Ybco Thin Film ◽  
Optical Reflectance ◽  
Voltage Contrast ◽  
Thin Film Resonators

Analysis of Integrated Circuits on the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 484-485
Author(s):  
John J. Imai
Keyword(s):  
Integrated Circuits ◽  
High Power ◽  
Integrated Circuit ◽  
Optical Microscope ◽  
Visual Observation ◽  
Depth Of Field ◽  
List Type ◽  
Type Number ◽  
Mode Of Operation ◽  
Voltage Contrast

The SEM plays an important role in the performance of failure analyses of Integrated Circuits. As the complexity and density of electrical functions increases on the silicon chip, the more it is nescessary to analyze the detailed characteristics of the failed device. The types of failures of interest are those that have marginal or catastrophic performance characteristics and show no obvious visual defects.Three aspects of the SEM capabilities will be discussed.Standard high power magnification operationVoltage Contrast mode of operationEmission X-ray analysis operationVarious physical characteristics of an Integrated Circuit can be viewed on the SEM. These characteristics are difficult to view on a high power optical microscope due to the depth of field limitations. These characteristics include the following.Oxide stepsMetalization profile over oxide stepsWire bond analysisEtched metalization characteristicsThe Voltage Contrast mode of operation allows direct visual observation of electrical activity on the surface of the silicon chip.

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