Copper coplanar waveguides in Si substrates for 10 GHz applications

2004 ◽  
Vol 22 (3) ◽  
pp. 847 ◽  
Author(s):  
R. E. Amaya ◽  
V. Levenets ◽  
N. G. Tarr ◽  
C. Plett
Keyword(s):  
Coplanar Waveguides ◽  
Si Substrates

scholarly journals Crosstalk Between Finite Ground Coplanar Waveguides Over Polyimide Layers for 3-D MMICs on Si Substrates

2004 ◽  
Vol 52 (4) ◽  
pp. 1292-1301 ◽  
Author(s):  
J. Papapolymerou ◽  
G.E. Ponchak ◽  
E. Dalton ◽  
A. Bacon ◽  
M.M. Tentzeris
Keyword(s):  
Coplanar Waveguides ◽  
Si Substrates

Coplanar waveguides fabricated by directly bonding metal foils to high-resistivity Si substrates

2021 ◽  
Author(s):  
Kenya Yonekura ◽  
Tasuku Kawamoto ◽  
Jianbo Liang ◽  
Eiji Shikoh ◽  
Koichi Maezawa ◽  
...  
Keyword(s):  
High Resistivity ◽  
Coplanar Waveguides ◽  
Si Substrates ◽  
Metal Foils

110 GHz Characterization of Coplanar Waveguides on GaN-on-Si Substrates

2010 ◽  
Vol 3 (12) ◽  
pp. 124101 ◽  
Author(s):  
Diego Marti ◽  
Mathias Vetter ◽  
Andreas R. Alt ◽  
Hansruedi Benedickter ◽  
C. R. Bolognesi
Keyword(s):  
Coplanar Waveguides ◽  
Si Substrates ◽  
Gan On Si

Power Performance of AlGaN/GaN HEMT's Grown on 6″ Si Substrates

2008 ◽  
Vol 1068 ◽  
Author(s):  
Joff Derluyn ◽  
Jo Das ◽  
Kai Cheng ◽  
Anne Lorenz ◽  
Domenica Visalli ◽  
...  
Keyword(s):  
Power Density ◽  
Output Power ◽  
Bias Voltage ◽  
Layer Structure ◽  
Trap Density ◽  
Buffer Layers ◽  
Coplanar Waveguides ◽  
Power Performance ◽  
Si Substrates

ABSTRACTAlGaN/GaN HEMT's were grown on 6″ Si <111> substrates and passivated using IMEC's in-situ SiN technique. The epitaxial growth was optimized to minimize RF losses due to the substrate-nitride interface while at the same time maintaining high buffer resistivity and low trap density.To assess RF losses of the epitaxial layer structure, coplanar waveguides were defined on places of the wafer where the top in-situ SiN and AlGaN has been etched away. The attenuation of the RF signals on the coplanar waveguides remained below 0.3dB/mm for frequencies up to 6GHz.The processing of HEMT's included mesa etching, the formation of TiAlMoAu ohmic contacts, 500nm long gates with source-connected field plates and an airbridge process. The gate fingers are 250µm wide, yielding a total gate periphery of 1.5mm for 6-finger devices and 5mm for the 20-finger version.The devices' RF power performance was characterised on-wafer. To avoid damage to the RF-probes, active load-pull measurements were performed in pulsed mode with a 100µs period under 10% and 30% duty cycle respectively. As there was no difference between the performance using different duty cycles, we conclude that the channel temperature reaches steady-state in less than 10µs.The 6-finger devices were operated in deep class AB operation mode but showed clear self-biasing effects. The bias voltage was changed from 30V to 60V in 10V increments. Under 60V bias, the devices provide an output power density of 7.9W/mm at 2GHZ with a PAE of 46% and 6.3W/mm at 4GHz with a PAE of 41%. The output power scales linearly with the bias voltage ranging from 30V to 60V, showing that there is no drain lag in the devices. We attribute this to the efficient surface passivation with the in-situ Si3N4 as well as to high crystal quality and hence the low trap density of the buffer layers. At 2GHz, the linear and saturated power gain are 22dB and 16.4dB respectively. An interesting observation is that the maximum gate current, even at power density levels of 7.9W/mm, remains below 50µA/mm which should prove beneficial for reliability.The larger 20-finger devices of 5mm total gate periphery reach a maximum absolute output power of 20W at a bias of 40V which represents the limit of our on-wafer measurement system.These results prove that the use of large area Si substrates is the only viable route forward for AlGaN/GaN HEMT's.

Low-Loss Coplanar Waveguides on GaN-on-Si Substrates

2018 ◽  
Vol 28 (10) ◽  
pp. 861-863 ◽  
Author(s):  
Lina Cao ◽  
Chien-Fong Lo ◽  
Hugues Marchand ◽  
Wanye Johnson ◽  
Patrick Fay
Keyword(s):  
Coplanar Waveguides ◽  
Low Loss ◽  
Si Substrates ◽  
Gan On Si

Interactions Between Al and Cr Thin Films

1976 ◽  
Vol 34 ◽  
pp. 638-639
Author(s):  
R. M. Anderson ◽  
T. M. Reith ◽  
M. J. Sullivan ◽  
E. K. Brandis
Keyword(s):  
Thin Films ◽  
Room Temperature ◽  
Vacuum System ◽  
Processing Temperature ◽  
Diffusion Couples ◽  
Electronic Circuits ◽  
Intermetallic Formation ◽  
Si Substrates ◽  
Aluminum Silicon

Thin films of aluminum or aluminum-silicon can be used in conjunction with thin films of chromium in integrated electronic circuits. For some applications, these films exhibit undesirable reactions; in particular, intermetallic formation below 500 C must be inhibited or prevented. The Al films, being the principal current carriers in interconnective metal applications, are usually much thicker than the Cr; so one might expect Al-rich intermetallics to form when the processing temperature goes out of control. Unfortunately, the JCPDS and the literature do not contain enough data on the Al-rich phases CrAl7 and Cr2Al11, and the determination of these data was a secondary aim of this work.To define a matrix of Cr-Al diffusion couples, Cr-Al films were deposited with two sets of variables: Al or Al-Si, and broken vacuum or single pumpdown. All films were deposited on 2-1/4-inch thermally oxidized Si substrates. A 500-Å layer of Cr was deposited at 120 Å/min on substrates at room temperature, in a vacuum system that had been pumped to 2 x 10-6 Torr. Then, with or without vacuum break, a 1000-Å layer of Al or Al-Si was deposited at 35 Å/s, with the substrates still at room temperature.

Electron Energy Analysis of Germanium and Silica Layers on Silicon Substrates

1975 ◽  
Vol 33 ◽  
pp. 96-97
Author(s):  
R. W. Ditchfield ◽  
A. G. Cullis
Keyword(s):  
Epitaxial Growth ◽  
Electron Energy ◽  
Silicon Substrates ◽  
Secondary Phases ◽  
Si Substrates ◽  
Transmission Electron ◽  
Layer Structures ◽  
Si Films ◽  
Electron Energy Loss ◽  
Growth Centres

An energy analyzing transmission electron microscope of the Möllenstedt type was used to measure the electron energy loss spectra given by various layer structures to a spatial resolution of 100Å. The technique is an important, method of microanalysis and has been used to identify secondary phases in alloys and impurity particles incorporated into epitaxial Si films.Layers Formed by the Epitaxial Growth of Ge on Si Substrates Following studies of the epitaxial growth of Ge on (111) Si substrates by vacuum evaporation, it was important to investigate the possible mixing of these two elements in the grown layers. These layers consisted of separate growth centres which were often triangular and oriented in the same sense, as shown in Fig. 1.

Defects in β-SiC thin films grown on α-SiC substrates

1988 ◽  
Vol 46 ◽  
pp. 568-569
Author(s):  
Karren L. More
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Lattice Mismatch ◽  
Chemical Vapor ◽  
Substrate Material ◽  
Growth Interface ◽  
Si Substrates ◽  
Thermal Expansion Coefficients ◽  
Device Applications ◽  
Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

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