Recent progress in 1×x-ray mask technology: Feasibility study using ASET-NIST format TaXN x-ray masks with 100 nm rule 4 Gbit dynamic random access memory test patterns

2001 ◽  
Vol 19 (6) ◽  
pp. 2416 ◽  
Author(s):  
Shinji Tsuboi ◽  
Yuusuke Tanaka ◽  
Toshiyuki Iwamoto ◽  
Hiroaki Sumitani ◽  
Yoshinori Nakayama
Keyword(s):  
Feasibility Study ◽  
Recent Progress ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Test ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
X Ray

Evaluation of Replicated Dynamic Random Access Memory Cell Patterns using X-Ray Lithography

1996 ◽  
Vol 35 (Part 1, No. 12B) ◽  
pp. 6452-6457 ◽  
Author(s):  
Yukiko Kikuchi ◽  
Ken-ichi Murooka ◽  
Shinji Sugihara ◽  
Soichiro Mitsui ◽  
Hiroshi Nomura ◽  
...  
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
X Ray ◽  
Cell Patterns

Sub-6F2 Charge Trap Dynamic Random Access Memory Using a Novel Operation Scheme

2006 ◽  
Author(s):  
Zongliang Huo ◽  
Seungjae Baik ◽  
Shieun Kim ◽  
In-seok Yeo ◽  
U-in Chung ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Charge Trap

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

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