Experimental and Numerical Investigation of Underfill Materials on Thermal Cycle Fatigue of Second Level Solder Interconnects Under Mean Temperature Conditions

2018 ◽  
Author(s):  
Maxim Serebreni ◽  
Patrick McCluskey ◽  
David Hillman ◽  
Nathan Blattau ◽  
Craig Hillman
Keyword(s):  
Solder Joints ◽  
Material Selection ◽  
Axial Loading ◽  
Critical Factor ◽  
Soft Materials ◽  
Solder Interconnects ◽  
Temperature Conditions ◽  
Mean Temperature ◽  
Fatigue Endurance ◽  
Underfill Material

With the larger size of Ball Grid Array (BGA) solder joints, the available volume for underfilling is significantly increased. Although the size of the solder joints and package dimension governs the volume of underfill material, the larger 2nd level solder interconnects are more susceptible to thermal fatigue with certain underfills and thermal profiles. In this study, BGA packages were underfilled with two dedicated underfill materials and two soft materials used as conformal coatings and encapsulants in electronic products. Each of the selected materials was subjected to two thermal profiles, one with low mean temperature and a second with a high mean temperature. The variation in mean cyclic temperature demonstrates the influence of temperature dependent behavior of each underfill material on the loads solder joints experience in a BGA package. Material characterization was performed on the package and underfill materials and incorporated into finite element models. The influence of underfill material glass transition temperature (Tg) was found to be a critical factor on fatigue endurance of solder interconnects. Fatigue crack orientation within solder joints were found to be aligned with axial (normal) direction for BGAs with high CTE underfill materials. Simulations determined the magnitude of axial loading associated with each underfill material properties responsible for reducing fatigue life. The results developed in this paper reveal the factors associated with reduced fatigue endurance of certain underfill materials under temperature profiles with mean temperature conditions and contribute to the development of new criteria of underfill material selection for 2nd level interconnects.

Studies on the storage of potatoes II. The temperature conditions inside potato clamps

1950 ◽  
Vol 40 (3) ◽  
pp. 199-226 ◽  
Author(s):  
E. M. Crook ◽  
D. J. Watson
Keyword(s):  
Air Temperature ◽  
Heat Production ◽  
First Year ◽  
Temperature Conditions ◽  
Mean Temperature ◽  
The Difference ◽  
Made In

Continuous records of the temperature of potatoes stored in clamps were made in 1942–3 (one clamp) and in 1943–4 (three clamps). In the first year, the temperatures at various positions in the clamp coverings were also recorded.The temperature at the middle of the potato heap showed a drift with time similar to that of mean air temperature. Deviations of mean air temperature from smooth trend, lasting for about a week, had no effect on the temperature of the potatoes; longerperiod deviations were reflected in the temperature of the potatoes after a lag of about a week. The difference in weekly mean temperature between potatoes and external air averaged about 1–5° C. in 1943–4. In 1942–3 it was greater, increasing to over 20° C. in April, because bacterial rotting of the potatoes following blight infection increased the rate of heat production and caused the clamp to collapse at the end of April.

Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies

2004 ◽  
Vol 127 (2) ◽  
pp. 120-126 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Numerical Study ◽  
Void Formation ◽  
Middle Layer ◽  
Molten Solder ◽  
Previous Theory ◽  
Solder Interconnects ◽  
Heating Profiles ◽  
High Lead

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb∕8Sn∕2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

Scaling Challenges of Semiconductor Packaging in the Era of Big Data

2013 ◽  
Vol 2013 (1) ◽  
pp. 000402-000407 ◽  
Author(s):  
Yasumitsu Orii ◽  
Akihiro Horibe ◽  
Kazushige Toriyama ◽  
Keiji Matsumoto ◽  
Hirokazu Noma ◽  
...  
Keyword(s):  
Big Data ◽  
Material Selection ◽  
Organic Substrate ◽  
Critical Element ◽  
3D Integration ◽  
Technology Innovations ◽  
Fine Pitch ◽  
3D Chip Stacking ◽  
Semiconductor Packaging ◽  
Underfill Material

In advent of multimedia, social media and Internet of Things, our world is exploding with enormous amount of data, so-called Big Data. The use of Big Data provides us with opportunities to bring solutions and innovations to variety of industries such as healthcare, energy, banking and automotive. On the other hand, the computing requirement to analyze this large volume of data is becoming higher than ever. The exascale computing is required in the Era of Big Data. In order to achieve this demand, further technology innovations for package scaling such as 3D-IC with TSV (through silicon via) are needed. The fine pitch die-to-die interconnection is a key element in increasing the total bandwidth in 3D integration. The important technologies in 3D integration include micro-bumping, thermally enhanced underfill materials and advanced interposers. Material selection for reliable fine-pitch interconnection has become a critical challenge in 3D chip stacking. Underfill material in die-to-die device is also a critical element in reducing total packaging stress and in enhancing vertical thermal conductivity. Low CTE high-density organic substrate is an emerging technology for 2.5D structure.

Thermal Fatigue Endurance of Lead-Free Composite Solder Joints over a Temperature Range of −55°C to 150°C

2009 ◽  
Vol 38 (6) ◽  
pp. 843-851 ◽  
Author(s):  
Olli Nousiainen ◽  
Tero Kangasvieri ◽  
Risto Rautioaho ◽  
Jouko Vähäkangas
Keyword(s):  
Thermal Fatigue ◽  
Composite Solder ◽  
Solder Joints ◽  
Lead Free ◽  
Temperature Range ◽  
Fatigue Endurance

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

Numerical Simulations of Electromigration and Stress Migration Driven Void Propagation in Pb Free Solder Interconnects

2011 ◽  
Author(s):  
Subramanya Sadasiva ◽  
Ganesh Subbarayan ◽  
Lei Jiang ◽  
Daniel Pantuso
Keyword(s):  
Flip Chip ◽  
Field Model ◽  
Solder Joints ◽  
Equations Of Motion ◽  
Phase Field Model ◽  
Solder Interconnects ◽  
Energy Stress ◽  
Current Densities ◽  
Void Propagation ◽  
Free Solder

Increasing miniaturization has led a significant increase in the current densities seen in flip-chip solder joints. This has made the study of failure in solder joints by void propagation due to electromigration and stress migration more important. In this study, we develop a phase field model for the motion of voids through a flip chip solder interconnect. We derive equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress and electric potential, taking into account both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using finite elements, coupled with a commercial finite element solver to solve for the fields driving the void motion.

Nonlinear Dynamic Analysis of Surface Mount Interconnects: Part I—Theory

1999 ◽  
Vol 121 (1) ◽  
pp. 8-11 ◽  
Author(s):  
C. Basaran ◽  
R. Chandaroy
Keyword(s):  
Dynamic Analysis ◽  
Solder Joints ◽  
Nonlinear Dynamic Analysis ◽  
Material Model ◽  
Microelectronics Packaging ◽  
Dynamic Stresses ◽  
Surface Mount ◽  
Solder Interconnects ◽  
Disturbed State Concept ◽  
Military Applications

Solder joints are commonly used in surface mount technology microelectronics packaging. It is well known that the dominant failure mode for solder joints is thermal fatigue. When semiconductor devices are used in a vibrating environment, such as in automotive and military applications, dynamic stresses contribute to the failure mechanism and in certain circumstances they can become the dominant failure cause. In this paper a unified constitutive model for Pb40/Sn60 solder joints is developed and then implemented in a finite element dynamic analysis procedure. The purpose of the material model and the implementation is to study the contribution of vibration induced strains to the fatigue life of solder interconnects in low cycle and high cycle fatigue. The proposed material model, which is based on the disturbed state concept (DSC), is used for a dynamic analysis of a solder joint in the following paper, Part II, Basaran and Chandaroy (1998).

scholarly journals A Computer-Aided Sustainable Modelling and Optimization Analysis of CNC Milling and Turning Processes

2018 ◽  
Vol 2 (4) ◽  
pp. 65 ◽  
Author(s):  
Karmjit Singh ◽  
Ibrahim Sultan
Keyword(s):  
Material Selection ◽  
Cutting Speed ◽  
Soft Materials ◽  
Numerical Control ◽  
Cnc Milling ◽  
Peripheral Milling ◽  
Optimization Analysis ◽  
Hard Materials ◽  
Production Stages ◽  
Modelling And Optimization

The sustainability of a manufacturing process can be measured by three main factors which impact both ecological and financial constraints. These factors are the energy required to achieve a specific job, the material utilized for the job, and the time taken to complete that job. These factors have to be quantified and analysed so that a proper manufacturing system can be designed to optimize process sustainability. For this purpose, a computer package, which utilizes life cycle inventory models has been presented for CNC (Computer Numerical Control) milling and turning processes. Based on utilization of resources and production stages, the job completion time for the turning and milling processes can be divided into process (i.e., machining), idle and basic times. As parameters are different for evaluating the process times, i.e., depth and width of cut in case of milling, initial and final diameters for turning, two different case studies are presented, one for each process. The effect of material selection on the sustainability factors has been studied for different processes. Our simulations show that highly dense and hard materials take more time in finishing the job due to low cutting speed and feed rates as compared to soft materials. In addition, face milling takes longer and consumes more power as compared to peripheral milling due to more retraction time caused by over travel distance and lower vertical transverse speeds than the horizontal transverse speed used in a peripheral retraction process.

Sign in / Sign up

Export Citation Format

Share Document