Thermal Investigation of Interconnect Technologies for GaAs RF Power Amplifier in Handheld Applications

Author(s):  
Tien-Yu Tom Lee ◽  
Victor A. Chiriac

Thermal simulation and infrared characterization are conducted to evaluate and compare the thermal performance of three interconnect options: wire bond, direct die attach, and flip chip interconnect. The test vehicle is a dual band RF PA module with low and high-band GaAs devices. As only one band is operated at a time, the focus is on the low-band GSM GaAs die. For direct die attach interconnect, the wire bond device is reused with all RF in/outs being connected from the backside of the GaAs device through individual vias in the device. The effects of through via design, solder attach material and thickness, and the thermal via layout in the substrate are evaluated. For flip chip interconnect, the original wire bond device was redesigned to accommodate metallic bumps for RF in/out, control and grounding. The ground bumps placed directly above the heat source area provide the main heat transfer path to the substrate. The size of the ground bumps, its material and the thermal vias layout in the substrate are investigated. Infrared thermal characterizations were conducted on both wire bond and direct die attach options to validate the simulations, with good agreement.

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000248-000271 ◽  
Author(s):  
Qun Wan

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.


2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.


Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.


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