High Resolution Die Stress Mapping Using Arrays of CMOS Sensors

2007 ◽  
Author(s):  
Yonggang Chen ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling
Keyword(s):  
High Resolution ◽  
Integrated Circuit ◽  
Sensor Arrays ◽  
Cmos Technology ◽  
Shear Stresses ◽  
Cmos Sensor ◽  
Bending Load ◽  
Die Stress ◽  
Stress Mapping ◽  
On Chip

This paper reports high resolution die stress measurements using a multiplexed array of 512 current mirror type CMOS piezoresistive FET stress sensor cells fabricated on an MOSIS tiny chip. Using 1.5 μm CMOS technology, a stress mapping resolution of 256 points/mm2 has been obtained, providing high spatial resolution mapping of the stress on the surface of the integrated circuit die. Driven by an on-chip counter, the sequentially scanned array efficiently maps the two-dimensional stress field. The sensor array is calibrated using a chip-on-beam calibration technique. These CMOS sensor arrays have been used to map stress on the die in the chip-on-beam configuration under four-point-bending load, in encapsulated chip-on-beam samples, and in DIP40 packages with cavities filled with underfill. The measured stress distribution agrees well with finite element simulation results, and permit smooth measurement of stress gradients on the surface of the integrated circuit die. The results give clear verification that the NMOS PiFET sensors are indeed responding to shear stresses.

CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits

2013 ◽  
Vol 13 (6) ◽  
pp. 2066-2076 ◽  
Author(s):  
Yonggang Chen ◽  
Richard C. Jaeger ◽  
Jeffrey C. Suhling
Keyword(s):  
High Resolution ◽  
Integrated Circuits ◽  
Sensor Arrays ◽  
Cmos Sensor ◽  
Die Stress ◽  
Stress Mapping

scholarly journals Efficiency Analysis of Low Power Class-E Power Amplifier

2014 ◽  
Vol 8 (5) ◽  
pp. 19
Author(s):  
Mousa Yousefi ◽  
Ziaadin Daie Koozehkanani ◽  
Jafar Sobhi ◽  
Hamid Jangi ◽  
Nasser Nasirezadeh
Keyword(s):  
Low Power ◽  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Efficiency Analysis ◽  
Simulation Results ◽  
On Chip ◽  
Power Class ◽  
Class E

This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated power loss and efficiency and MATLAB evaluations. Considering the analysis, the proposed power amplifier shows about 13 % improvement in power effiency at 400 MHz and -2 dBm output power. It is simulated in 0.18 ?m CMOS technology.

FULL-CHIP POWER-SUPPLY NOISE: THE EFFECT OF ON-CHIP POWER-RAIL INDUCTANCE

2002 ◽  
Vol 12 (02) ◽  
pp. 573-582 ◽  
Author(s):  
C. W. FOK ◽  
D. L. PULFREY
Keyword(s):  
Power Supply ◽  
Integrated Circuit ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Power Supply Noise ◽  
Ir Drop ◽  
Supply Noise ◽  
On Chip ◽  
Simultaneous Switching

The importance of on-chip power-rail inductance in generating delta-I power-supply noise is examined in this paper using systematic circuit simulation of the complete integrated-circuit power net. This source of noise is compared to the resistive IR drop in the net, and to the delta-I noise due to both high-inductance- and low-inductance-bonding packages. Results are presented for a typical on-chip power net in 0.18 μm CMOS technology, and it is demonstrated that the inductance of this on-chip power net is the dominant contributor to the full-chip power-supply noise. The simultaneous switching events which produce the triggering current transients for the delta-I noise are taken to arise from core-logic switching; the mitigating, de-coupling role of the capacitance of non-switching gates within the core-logic block is considered.

Integrated Circuit Device Repair Using FIB System: Tips, Tricks, and Strategies

1999 ◽  
Author(s):  
K. N. Hooghan ◽  
K. S. Wills ◽  
P.A. Rodriguez ◽  
S.J. O’Connell
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Dead Reckoning ◽  
Physical Damage ◽  
Art Form ◽  
Metal Levels ◽  
Potential Damage ◽  
On Chip ◽  
Beam Currents

Abstract Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Transcriptome comparisons of in vitro intestinal epithelia grown under static and microfluidic gut-on-chip conditions with in vivo human epithelia

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Kornphimol Kulthong ◽  
Guido J. E. J. Hooiveld ◽  
Loes Duivenvoorde ◽  
Ignacio Miro Estruch ◽  
Victor Marin ◽  
...  
Keyword(s):  
Gene Expression ◽  
Culture Conditions ◽  
Gene Set Enrichment Analysis ◽  
Shear Stresses ◽  
Static Culture ◽  
Dynamic Culture ◽  
Intestinal Segments ◽  
On Chip

AbstractGut-on-chip devices enable exposure of cells to a continuous flow of culture medium, inducing shear stresses and could thus better recapitulate the in vivo human intestinal environment in an in vitro epithelial model compared to static culture methods. We aimed to study if dynamic culture conditions affect the gene expression of Caco-2 cells cultured statically or dynamically in a gut-on-chip device and how these gene expression patterns compared to that of intestinal segments in vivo. For this we applied whole genome transcriptomics. Dynamic culture conditions led to a total of 5927 differentially expressed genes (3280 upregulated and 2647 downregulated genes) compared to static culture conditions. Gene set enrichment analysis revealed upregulated pathways associated with the immune system, signal transduction and cell growth and death, and downregulated pathways associated with drug metabolism, compound digestion and absorption under dynamic culture conditions. Comparison of the in vitro gene expression data with transcriptome profiles of human in vivo duodenum, jejunum, ileum and colon tissue samples showed similarities in gene expression profiles with intestinal segments. It is concluded that both the static and the dynamic gut-on-chip model are suitable to study human intestinal epithelial responses as an alternative for animal models.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

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