Evaluation of Two-Phase Cold Plate for Cooling Electric Vehicle Power Electronics

2011 ◽  
Author(s):  
Peng Wang ◽  
Patrick McCluskey ◽  
Avram Bar-Cohen
Keyword(s):  
Power Electronics ◽  
Electric Vehicle ◽  
Thermal Management ◽  
High Performance ◽  
Single Phase ◽  
Low Cost ◽  
Critical Issue ◽  
System Level ◽  
Cold Plate ◽  
Two Phase

Rapid increases in the power ratings and continued miniaturization of semiconductor devices have pushed the heat flux of power electronics well beyond the range of conventional thermal management techniques, and thus maintaining the IGBT temperature below a specified limit has become a critical issue for thermal management of electric vehicle power electronics. Although two-phase cold plates have been identified as a very promising high flux cooling solution, they have received little attention for cooling of power electronics. In this work, a first-order analytical model and a system-level thermal simulation are used to compare single-phase and two-phase cold plate cooling for Toyota Prius motor inverter, consisting of 12 pairs of IGBT’s and diodes. Our results demonstrate that with the same cold plate geometry, R134a two-phase cooling can substantially reduce the maximum IGBT temperature, operate all the IGBT’s at very uniform temperatures, and lower the pumping power and flow rate in comparison to single-phase cold plate cooling. These results suggest that two-phase cold plate can be developed as a low-cost, small-volume, and high-performance cooling solution to improve system reliability and conversion efficiency for electric vehicle power electronics.

Two-Phase Liquid Cooling for Thermal Management of IGBT Power Electronic Module

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Peng Wang ◽  
Patrick McCluskey ◽  
Avram Bar-Cohen
Keyword(s):  
Power Electronics ◽  
Thermal Management ◽  
Single Phase ◽  
Heat Dissipation ◽  
Heat Fluxes ◽  
System Level ◽  
Cooling Power ◽  
Cold Plate ◽  
Two Phase ◽  
Cold Plates

Recent trends including rapid increases in the power ratings and continued miniaturization of semiconductor devices have pushed the heat dissipation of power electronics well beyond the range of conventional thermal management solutions, making control of device temperature a critical issue in the thermal packaging of power electronics. Although evaporative cooling is capable of removing very high heat fluxes, two-phase cold plates have received little attention for cooling power electronics modules. In this work, device-level analytical modeling and system-level thermal simulation are used to examine and compare single-phase and two-phase cold plates for a specified inverter module, consisting of 12 pairs of silicon insulated gate bipolar transistor (IGBT) devices and diodes. For the conditions studied, an R134a-cooled, two-phase cold plate is found to substantially reduce the maximum IGBT temperature and spatial temperature variation, as well as reduce the pumping power and flow rate, in comparison to a conventional single-phase water-cooled cold plate. These results suggest that two-phase cold plates can be used to substantially improve the performance, reliability, and conversion efficiency of power electronics systems.

Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat Flux

2010 ◽  
Vol 132 (4) ◽  
Author(s):  
Yoon Jo Kim ◽  
Yogendra K. Joshi ◽  
Andrei G. Fedorov ◽  
Young-Joon Lee ◽  
Sung-Kyu Lim
Keyword(s):  
Integrated Circuits ◽  
Mass Flow Rate ◽  
Thermal Management ◽  
Mass Flow ◽  
Flow Rate ◽  
Single Phase ◽  
Hot Spot ◽  
Three Dimensional ◽  
Two Phase ◽  
Two Phase Cooling

It is now widely recognized that the three-dimensional (3D) system integration is a key enabling technology to achieve the performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D-stacked ICs, the interlayer microfluidic cooling scheme is adopted and analyzed in this study focusing on a single cooling layer performance. The effects of cooling mode (single-phase versus phase-change) and stack/layer geometry on thermal management performance are quantitatively analyzed, and implications on the through-silicon-via scaling and electrical interconnect congestion are discussed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that the large internal pressure and the pumping pressure drop are significant limiting factors, along with significant mass flow rate maldistribution due to the presence of hot-spots. Nevertheless, two-phase cooling using R123 and R245ca refrigerants yields superior performance to single-phase cooling for the hot-spot fluxes approaching ∼300 W/cm2. In general, a hybrid cooling scheme with a dedicated approach to the hot-spot thermal management should greatly improve the two-phase cooling system performance and reliability by enabling a cooling-load-matched thermal design and by suppressing the mass flow rate maldistribution within the cooling layer.

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

FPGA-Based Test Equipment for System-Level MEMS Switch Series

2015 ◽  
Vol 645-646 ◽  
pp. 572-576
Author(s):  
Peng Liu ◽  
Wen Zhong Lou ◽  
Yu Fei Lu ◽  
Xin Yu Feng
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Original Data ◽  
Test Equipment ◽  
System Level ◽  
Mems Switch ◽  
Real Time Analysis ◽  
Embedded Algorithms ◽  
Equipment System

A high-performance, low-cost test equipment system for characterization of MEMS switch is to be proposed in this paper, and the purpose is set to master the fundament of the embedded algorithms of the wafer and system production testing. The team has implemented the real-time analysis for MEMS switch, proving the feasibility of the design, based on the original data collected during the dedicated tests, applying the microsystem hardware designed and assembled by the research team, as well as the embedded software. At the end, the framework of the system platform in the future is described.

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