BPM: A Bad Page Management Strategy for the Lifetime Extension of Flash Memory

Author(s):  
Wei Debao ◽  
Qiao Liyan ◽  
Zhang Peng ◽  
Peng Xiyuan

The lifetime of NAND flash is highly restricted by bit error rate (BER) which would exponentially increase with the number of program/erase cycles. While the error correcting codes (ECC) can only provide a limited error correction ability to tolerate the bit errors. To face this challenge, a novel bad page management (BPM) strategy is proposed to extend the lifetime of NAND flash based on the experimental observations in our hardware-software co-designed experimental platform. The experimental observations indicate that retention error is the dominant type of NAND flash errors, which is caused by the charge leakage in memory cells over time. The BER distribution of retention error shows distinct variance in different pages. The key idea of BPM is to excavate lifetime potency of each page in a block by introducing the fine granularity bad page management instead of the coarse granularity bad block management. In addition, to balance the lifetime enhancement and the storage capacity degradation, a configurable threshold of bad page management (CT-BPM) strategy is proposed to utilize in the storage capacity highly demanded applications. The experimental results show that BPM can provide dozens of times (about 35 times for 3x-nm NAND flash) average lifetime extension without additional hardware cost, while experiencing at most 5% degradation in writing speed.

2020 ◽  
Vol 20 (7) ◽  
pp. 4138-4142
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nagyong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth −0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth −0.5 to Vth+1.


2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.


Author(s):  
Ting Cheng ◽  
Jianquan Jia ◽  
Lei Jin ◽  
Xinlei Jia ◽  
Shiyu Xia ◽  
...  

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