Effects of Stacked Layers and Stacked Configurations on Wire Sweep and Wire Sag of Advanced Overhang/Pyramid Stacked Packages

2017 ◽  
Vol 139 (4) ◽  
Author(s):  
Huang-Kuang Kung ◽  
Chi-Lung Hsieh

Overhang and/or pyramid stacked packages are the trend in the semiconductor industry. As the stacked layers increase drastically, the wire sweep and wire sag problems become more and more serious. Based on some types of frequently used stacked configurations, their corresponding wire sweep and wire sag stiffness and deflections are investigated for extra-high stacked layers. Two typical profiles of Q_loop and S_loop wire bonds are included in this study. However, wire sweep and wire sag have to be considered in two different design aspects. For wire sweep, we have the conclusion that the maximum wire sweep deflections always occur near the central segment of a wire bond. As for the wire sag, the maximum wire sag may take place in the center region of the straight portion of a wire bond. The result shows that the deflections of wire sag can be reduced significantly by simply shifting the position of the kink or bend created within a wire bond. Finally, we have concluded that a stacked configuration with smallest bond span may be the preferred selection for the concerns of wire sweep and wire sag issues.

2012 ◽  
Vol 2012 (1) ◽  
pp. 000665-000676
Author(s):  
Thomas F. Marinis ◽  
Joseph W. Soucy

The pitch of wire bond connections is decreasing to meet the need for higher interconnect densities, while at the same time, the ratio of wire length to diameter is increasing, which lowers the mechanical resonant frequency of the wire. In many applications in which MEMS sensors are coupled with ASIC front end electronics, the bonded wires can be subjected to a wide frequency spectrum of mechanical vibrations. One potential consequence is that the parasitic capacitances of the sensor could vary dynamically at a magnitude comparable to that of the sensor signal. In extreme cases, intermittent shorts or fatigue failures of the wire bonds could occur. A recent paper by Barber et. al, showed that wire bonds carrying alternating currents in a strong magnetic field could suffer fatigue failure.[1] Their analysis and experiments focused on simple loop geometries. In many applications, more complex wire bond geometries are used to minimize loop height and obtain dense wiring in stacked chip configurations. These geometries give rise to many more vibration modes with unique resonant frequencies and displaced shapes. We have used simple analytical beam models in conjunction with finite element models (FEM) to study various wire bond configurations subject to mechanical vibratory excitation. We focused on the effects of overall wire length and geometric shape on resonant modes. The finite element models were also used to calculate the capacitance between adjacent wires subject to mechanical excitation at one or more of their resonant frequencies. We show that there is an apparent shift in the time averaged capacitive coupling that increases with increasing vibration amplitude.


1991 ◽  
Vol 113 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir ◽  
L. T. Manzione

An analytical stress model is developed for the evaluation of flow induced stresses in wire bonds of plastic packages during molding. We limit our analysis to the stresses acting in the plane of a wire bond. These stresses can possibly result in liftoff of the ball bond from the bonding pad of the integrated circuit. The main purpose of the analysis is to evaluate the effect of the wire bond configuration. It is shown that the stresses in wire bonds are proportional to the square of the ratio of the wire-bond span to the diameter of the wire. This explains the difficulty in molding assemblies with long wire bond spans. We also showed that wire configurations, characterized by nonzero slope angles at the ends, result in lower stresses than conventional wire shapes, where the wedge bond to the electric lead forms a zero angle. The obtained results are useful when designing plastic package assemblies and/or choosing the appropriate wire bond loop height and span.


2016 ◽  
Vol 33 (1) ◽  
pp. 53-60 ◽  
Author(s):  
Hui Yuen Peng ◽  
Mutharasu Devarajan ◽  
Teik Toon Lee ◽  
David Lacey

Purpose – The purpose of this paper is to investigate the reliability of wire bonds with three varying ball bond diameters, which are ball bonded with three different sizes of gold wires in light-emitting diode (LED) package under high-temperature environment. In automotive applications, “lifted ball bond” issue is a potential critical point for LED device reliability, as the wire bonds are usually stressed under high operating temperature during their lifetime. Moreover, the reliability of wire bonds in recent LED production has fallen under scrutiny due to the practice of reducing wire diameters to cut down production costs. Design/methodology/approach – Three gold wires with sizes of 2, 1.5 and 1 mm were ball bonded on the LED chip bond pad via thermosonic wire bonding method to produce three different ball bond diameters, that is, 140, 120 and 100 μm, respectively. The reliability of these wire bond samples was then studied by performing isothermal aging at 200°C for the time interval of 30, 100 and 500 hours. To validate hypotheses based on the experimental data, COMSOL Multiphysics simulation was also applied to study the thermal stress distribution of wire bond under an elevated temperature. Findings – Experimental results show that the interfacial adhesion of wire bond degrades significantly after aging at 200°C for 500 hours, and the rate of interfacial degradation was found to be more rapid in the wire bond with smaller ball bond diameter. Experimental results also show that ball bonds randomly elongate along an axis and deforms into elliptical shapes after isothermal aging, and ball bonds with smaller diameters develop more obvious elongations. This observation has not been reported in any previous studies. Simulation results show that higher thermal stress is induced in the wire bond with the decrease of ball bond diameter. Practical implications – The reliability study of this paper provides measurements and explanation on the effects of wire diameter downsizing in wire bonds for automotive application. This is applicable as a reliability reference for industries who intend to reduce their production costs. Other than that, the analysis method of thermal stresses using COMSOL Multiphysics simulations can be extended by other COMSOL Multiphysics users in the future. Originality/value – To resolve “lifted ball bond” issue, optimization of the bond pad surface quality and the wire bond parameter has been studied and reported in many studies, but the influence of ball bond diameter on wire bond reliability is rarely focused. Moreover, the observation of ball bonds randomly elongate and deform more into elliptical shape, and ball bond with smaller diameter has the highest elongation after isothermal aging also still has not been reported in any previous studies.


2018 ◽  
Vol 12 (4) ◽  
pp. 4275-4284
Author(s):  
S. Shariza ◽  
T. Joseph Sahaya Anand ◽  
A. R. M. Warikh ◽  
Lee Cher Chia ◽  
Chua Kok Yau ◽  
...  

Bond strength evaluation of wire bonding in microchips is the key study in any wire bonding mechanism. The quality of the wire bond interconnection relates very closely to the reliability of the microchip during performance of its function in any application. In many reports, concerns regarding the reliability of the microchip are raised due to formation of void at the wire-bond pad bonding interface, predominantly after high temperature storage (HTS) annealing conditions. In this report, the quality of wire bonds prepared at different conditions, specifically annealed at different HTS durations are determined by measurements of the strength of the interface between the bond wire and the bond pad. The samples are tested in pull test and bond shear test. It was observed that the higher bonding temperature as well as the longer duration of HTS increased the bond strength. This is represented through the analysis of the measurements of ball shear strength. This is due to the fact that higher bonding temperature and longer HTS promoted better growth of the Cu-Al IMC layer. A transmission electron microscopy - energy dispersive X-ray analysis (TEM-EDX) has been carried out to observe the formation of the Cu-Al IMC layer in the sample.    


2013 ◽  
Vol 2013 (1) ◽  
pp. 000331-000335
Author(s):  
Richard C. Garcia ◽  
Josef Sedlmair (F&K Delvotec)

In hybrid electronics, it is a standard practice to perform 100% wire bond pull testing to ensure robust wire bonding of the components. The principle behind Mil-STD-883 method 2023.5 compliant wire bond pull testing is to position the hook underneath the wire and either pull until the wire breaks or, alternatively, pull to a predefined force. With high density layouts, small component geometry or staggered wire bonds, it has been a challenge for manufacturing operations to maintain consistency in “manually” placing the wirepull hook on wires with varying height, looping profiles and wire distances. The influence of loop height and wire distance is a significant factor in determining the true wire pull strength. A low wire loop will result in lower measured pull strength, while a higher loop will result in higher pull strength. Therefore, if we can accurately quantify the loop height and profile then we can place the wirepull hook in the optimum position for pulling. In this study we will demonstrate how the “parallelogram of forces” can affect wirepull measurements. With the advent of the current generation of automated wirebond pull testers, we can accurately determine the appropriate correction factor(s) for varying loop heights in order to position the wirepull hook at the precise location necessary for accurate and meaningful results. In addition, with real time yield monitoring, the new pull testers are capable of locating and identifying missing wires that can often be attributed to the high density of today's circuit designs.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000486-000493 ◽  
Author(s):  
Aditi Mallik ◽  
Roger Stout

For high power IC chips, as device size inevitably decreases, the wire diameter unfortunately must decrease due to the need of finer pitch wires. Fusing or melting of wirebonds thus increasingly becomes one of the potential failure issues for such IC's. Experiments were performed under transient loads on dummy packages having aluminum, gold, or copper wires of different dimensions. A finite element model was constructed that correlates very well with the observed maximum operating currents for such wirebonds under actual experimental test conditions. A qualitative observation of typical current profiles, as fusing conditions were approached, was that current would reach a maximum value very early in the pulse, and then fall gradually. One goal achieved through the modeling was to show that the current in the wire falls with time due to the heating of the wire material. Correspondingly, the wire reaches the melting temperature not at the peak current but rather at the end of pulse. Further, modeling shows that knowledge of external resistance and inductance of the experimental set up are highly significant in determining the details of a fusing event, but if known along with the temperature-dependent wire properties, the simulation can predict the correct voltage and current response of the part with 2% error. On the other hand, lack of external circuit characteristics may lead to completely incorrect results. For instance, the assumption that current is constant until the wire heats to fusing temperature, or that current and temperature both rise monotonically to maximum values until the wire fuses, are almost certain to be wrong. The work has been carried out for single pulse events as well as pulse trains.


2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000061-000065
Author(s):  
David Shaddock ◽  
Liang Yin

Abstract Test results for a range of potting materials for encapsulation of wire bonds for a high temperature multi-chip module is presented. The potting materials include gels and more rigid epoxies, silicone, and silicone-ceramic materials. The materials were initially screened based on ease of processing, cracking, and weight loss at 200, 225, and 250°C. Materials that performed well after this initial screening were tested for insulation resistance at 200, 225, and 250°C and wire bonds were encapsulated for thermal cycled at −55 to 200°C and −55 to 250°C.


2012 ◽  
Vol 2012 (1) ◽  
pp. 001137-001142 ◽  
Author(s):  
Ilyas Mohammed

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000425-000429 ◽  
Author(s):  
Richard C. Garcia

Thick film technology is based on a paste containing glass frit that is screen printed and fused at high temperature onto various ceramic substrate materials. Softening or melting this glassy frit forms a cohesive layer, binding the conductors, resistors or dielectric materials to the ceramic. The dynamics of the printing process and inherent number of associated variables negatively impact the uniformity of the fired surface on a micro scale, which can lead to variation in the wire bonding process. Other processes associated with thick film substrate fabrication can cause problems as well. Laser trimming is used to adjust the value of printed resistors to meet design requirements. This ablation of printed resistors by high–powered pulse laser leaves a halo of debris and contamination on the ceramic substrate, which can cause wire bond lifting. In this paper, we will demonstrate a way to eliminate these problems using a bonding technique called Stand- Off Stitch bonding (SOS). This wire bond type is formed by first placing a ball bump at the second bond, or stitch, location on the thick film substrate, and then forming a normal wire that terminates on that bump. This places two ball bumps at each end of the wire, similar to a security bond. However, the ball bump is located under the stitch instead of on top. This SOS wire bond technique is compliant with the MIL-STD- 883 for a compound bond, where one bond is placed on top of another bond. With the gold bump placed on top of the gold thick film pad, the bump acts as a foundation for the stitch bond, providing a wider contact area and clean bond surface to secure a reliable stitch bond interconnect. With this change, an abrupt improvement to the resultant destruct wire pull tests can be achieved, promoting a robust, controlled process for wire bond interconnects.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000687-000694
Author(s):  
Caroline Beelen-Hendrikx ◽  
Coen Tak

Advantages of silicon-based sensors are compatibility with CMOS, improved robustness and reliability, smaller size and reflow compatibility. Biosensors that use an electrical measurement principle need electrical connections and fluidic access to the die. This only works when the electrical interconnects are kept clean of biofluid and when the package is compatible with the biofluids, receptor chemicals and other sensor elements. In addition, the package needs to be very cheap. A simple plastic overmolded package with a hole in the compound at the sensor location is an effective solution. RFID sensors also need direct die access for gass and pH sensing. They require the integration of processor, memory, clock, battery and antenna. The package format depends on the application. For checking the quality of perishables during transport or in a store, a disposable flexible tag is needed whereas for smart building sensors, a plastic module is more appropriate. For the sensor tag, a flexible substrate and flip chip bare dies are used. Direct die access is realized by an opening in the flex. Battery and antenna are printed on the flex. Automotive sensors that are used under the hood need to cope with very high operating temperatures with peak temperatures of up to 200 °C and they need to be delamination free. The critical points in the standard plastic packages used today are the molding compound and the wire-bonds. Standard packages can be used up to 150 °C. For higher temperatures, the molding compound and the wire-bond interconnect are being improved.


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