Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Herman Oprins ◽  
Vladimir Cherman ◽  
Geert Van der Plas ◽  
Joeri De Vos ◽  
Eric Beyne
Keyword(s):  
Power Distribution ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Three Dimensional ◽  
Lateral Spreading ◽  
Circuit Board ◽  
Experimental Characterization ◽  
Test Chip ◽  
Conductivity Increase

In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.

Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages

2015 ◽  
Author(s):  
Herman Oprins ◽  
Vladimir Cherman ◽  
Geert Van der Plas ◽  
Joeri De Vos ◽  
Eric Beyne
Keyword(s):  
Power Distribution ◽  
Hot Spot ◽  
Lateral Spreading ◽  
Experimental Characterization ◽  
Test Chip ◽  
Conductivity Increase ◽  
Thermal Conductivity Increase ◽  
Equivalent Properties ◽  
Lateral Heat

In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the epoxy mold compound and the die-die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the trade-off between the stand-off height reduction and the underfill thermal conductivity increase in order to reduce the inter die thermal resistance.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

Three Dimensional Detection of the via in the PCB CT Image Using Morphology Operation

2015 ◽  
Vol 752-753 ◽  
pp. 1406-1412
Author(s):  
Lei Zeng ◽  
Jian Chen ◽  
Han Ning Li ◽  
Bin Yan ◽  
Yi Fu Xu ◽  
...  
Keyword(s):  
Nondestructive Testing ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Detection Algorithm ◽  
Circuit Board ◽  
Dimensional Structure ◽  
Three Dimension ◽  
Shape Information ◽  
Printed Circuit ◽  
Testing Technology

In modern industry, the nondestructive testing of printed circuit board (PCB) can prevent effectively the system failure and is becoming more and more important. As a vital part of the PCB, the via connects the devices, the components and the wires and plays a very important role for the connection of the circuits. With the development of testing technology, the nondestructive testing of the via extends from two dimension to three dimension in recent years. This paper proposes a three dimensional detection algorithm using morphology method to test the via. The proposed algorithm takes full advantage of the three dimensional structure and shape information of the via. We have used the proposed method to detect via from PCB images with different size and quality, and found the detection performances to be very encouraging.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENTTM Software

2013 ◽  
Vol 795 ◽  
pp. 603-610 ◽  
Author(s):  
Mohamed Mazlan ◽  
A. Rahim ◽  
M.A. Iqbal ◽  
Mohd Mustafa Al Bakri Abdullah ◽  
W. Razak ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Fluid Dynamic ◽  
Three Dimensional ◽  
Circuit Board ◽  
Junction Temperature ◽  
Inlet Velocity ◽  
Chip Carrier ◽  
Flow Through ◽  
Package Density ◽  
Heat And Fluid Flow

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

scholarly journals Variable-Temperature Noise Characterization of N-MOSFETs Using an In-Situ Broadband Amplifier

2021 ◽  
Author(s):  
Kenji Ohmori ◽  
Shuhei Amakawa
Keyword(s):  
Shot Noise ◽  
Printed Circuit Board ◽  
Noise Figure ◽  
Variable Temperature ◽  
Low Noise ◽  
Broadband Noise ◽  
Circuit Board ◽  
Low Frequencies ◽  
Cryogenic Chamber

Characterization of broadband noise of MOSFETs from room temperature down to 120 K in fine temperature steps is presented. A MOSFET is mounted on a reusable printed circuit board vehicle with a built-in low-noise amplifier, and the vehicle is loaded into a cryogenic chamber. The vehicle allows noise measurement in the frequency range from 50 kHz to 100 MHz. At low frequencies, it enables extraction of activation energies associated with electron trapping sites. At high frequencies, as has been suggested by noise figure measurements, the white noise of MOSFETs is shown to be dominated by the shot noise, which has much weaker temperature dependence than the thermal noise. The shot noise will be a problematic noise source in broadband RF CMOS circuits operating at cryogenic temperatures.<div><br></div>

Virtual Ground Fence: A Simple Method for Protection against High Frequency Simultaneous Switching Noise

2012 ◽  
Vol 2012 (1) ◽  
pp. 001081-001084 ◽  
Author(s):  
Jesse Bowman ◽  
A. Ege Engin
Keyword(s):  
Power Distribution ◽  
Distribution System ◽  
Power Efficiency ◽  
Printed Circuit Board ◽  
Supply Voltage ◽  
Circuit Board ◽  
Voltage Source ◽  
Accurate Estimation ◽  
Simple Method ◽  
Power Distribution System

When integrating sensitive RF analog devices with complex VLSI digital components, simultaneously switching drivers cause supply voltage fluctuations which can propagate both horizontally and vertically between the power/ground planes. The same voltage source on a printed circuit board can be shared to increase power efficiency and reduce space used. In order to accomplish this, on board filtering is needed to isolate the noise between these two types of devices for proper operation. Hence, accurate estimation and improvement of the performance of power/ground planes is critical in a mixed-signal system. We present a new method to minimize the noise transfer at high frequencies to the power distribution system, called the Virtual Ground Fence. At its basic level, the Virtual Ground Fence consists of quarter-wave transmission-line stubs that act as short circuits between power and ground planes at their design frequency. We will present various configurations of Virtual Ground Fence for different coupling scenarios.

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

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