Fatigue Damage Modeling Techniques for Textile Composites: Review and Comparison With Unidirectional Composite Modeling Techniques

2015 ◽  
Vol 67 (2) ◽  
Author(s):  
R. D. B. Sevenois ◽  
W. Van Paepegem
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
Fatigue Loading ◽  
High Volume ◽  
Mechanical Tests ◽  
Unidirectional Composite ◽  
Textile Composites ◽  
The State ◽  
Simulation Techniques ◽  
Modeling Techniques

Composite structural parts have been successfully introduced in high performance industries. Nowadays, also lower performance, high volume production industries are looking for the application of composites in their products. Especially attractive are textile composites (woven, braided, etc.) because of their better drapability and higher resistance to out-of-plane and dynamic loads. Currently, however, extensive mechanical tests are needed to properly design a composite structure. This is a requirement the large volume industries typically do not have the resources nor the time for. Reducing the need for structural tests can only be done if reliable simulation techniques are available. Simulation techniques for fatigue loading are particularly interesting because products generally have to perform their function over a period of time. For the textile structural composites concerned in this paper, some notable modeling techniques have been developed over the past 15 years. These techniques are presented here and the state of the art is established together with insights for future development by comparing the state of the art with the modeling techniques for laminates from unidirectional (UD) laminae.

Advancing the state of the art in high-performance logic and array technology

1992 ◽  
Vol 36 (5) ◽  
pp. 821-828 ◽  
Author(s):  
K. H. Brown ◽  
D. A. Grose ◽  
R. C. Lange ◽  
T. H. Ning ◽  
P. A. Totta
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
The State ◽  
Array Technology

BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization

2021 ◽  
Vol 14 (4) ◽  
pp. 1-28
Author(s):  
Tao Yang ◽  
Zhezhi He ◽  
Tengchuan Kou ◽  
Qingzheng Li ◽  
Qi Han ◽  
...  
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
The State ◽  
Optimization Approach ◽  
Quantization Scheme ◽  
Model Accuracy ◽  
Sparsity Pattern ◽  
Computing Platform ◽  
Energy Efficiency Improvement ◽  
Mixed Precision

Field-programmable Gate Array (FPGA) is a high-performance computing platform for Convolution Neural Networks (CNNs) inference. Winograd algorithm, weight pruning, and quantization are widely adopted to reduce the storage and arithmetic overhead of CNNs on FPGAs. Recent studies strive to prune the weights in the Winograd domain, however, resulting in irregular sparse patterns and leading to low parallelism and reduced utilization of resources. Besides, there are few works to discuss a suitable quantization scheme for Winograd. In this article, we propose a regular sparse pruning pattern in the Winograd-based CNN, namely, Sub-row-balanced Sparsity (SRBS) pattern, to overcome the challenge of the irregular sparse pattern. Then, we develop a two-step hardware co-optimization approach to improve the model accuracy using the SRBS pattern. Based on the pruned model, we implement a mixed precision quantization to further reduce the computational complexity of bit operations. Finally, we design an FPGA accelerator that takes both the advantage of the SRBS pattern to eliminate low-parallelism computation and the irregular memory accesses, as well as the mixed precision quantization to get a layer-wise bit width. Experimental results on VGG16/VGG-nagadomi with CIFAR-10 and ResNet-18/34/50 with ImageNet show up to 11.8×/8.67× and 8.17×/8.31×/10.6× speedup, 12.74×/9.19× and 8.75×/8.81×/11.1× energy efficiency improvement, respectively, compared with the state-of-the-art dense Winograd accelerator [20] with negligible loss of model accuracy. We also show that our design has 4.11× speedup compared with the state-of-the-art sparse Winograd accelerator [19] on VGG16.

Towards Update-Efficient and Parallel-Friendly Content-Based Indexing Scheme in Cloud Computing

2018 ◽  
Vol 12 (02) ◽  
pp. 191-213
Author(s):  
Nan Zhu ◽  
Yangdi Lu ◽  
Wenbo He ◽  
Hua Yu ◽  
Jike Ge
Keyword(s):  
Cloud Computing ◽  
State Of The Art ◽  
High Volume ◽  
Data Partitioning ◽  
The State ◽  
Computing Systems ◽  
Indexing System ◽  
Indexing Method ◽  
Concurrent User ◽  
Art Research

The sheer volume of contents generated by today’s Internet services is stored in the cloud. The effective indexing method is important to provide the content to users on demand. The indexing method associating the user-generated metadata with the content is vulnerable to the inaccuracy caused by the low quality of the metadata. While the content-based indexing does not depend on the error-prone metadata, the state-of-the-art research focuses on developing descriptive features and misses the system-oriented considerations when incorporating these features into the practical cloud computing systems. We propose an Update-Efficient and Parallel-Friendly content-based indexing system, called Partitioned Hash Forest (PHF). The PHF system incorporates the state-of-the-art content-based indexing models and multiple system-oriented optimizations. PHF contains an approximate content-based index and leverages the hierarchical memory system to support the high volume of updates. Additionally, the content-aware data partitioning and lock-free concurrency management module enable the parallel processing of the concurrent user requests. We evaluate PHF in terms of indexing accuracy and system efficiency by comparing it with the state-of-the-art content-based indexing algorithm and its variances. We achieve the significantly better accuracy with less resource consumption, around 37% faster in update processing and up to 2.5[Formula: see text] throughput speedup in a multi-core platform comparing to other parallel-friendly designs.

scholarly journals Resilient gossip-inspired all-reduce algorithms for high-performance computing: Potential, limitations, and open questions

2018 ◽  
Vol 33 (2) ◽  
pp. 366-383
Author(s):  
Marc Casas ◽  
Wilfried N Gansterer ◽  
Elias Wimmer
Keyword(s):  
Fault Tolerance ◽  
High Performance Computing ◽  
High Performance ◽  
State Of The Art ◽  
The State ◽  
Reduction Algorithm ◽  
Data Corruption ◽  
Parallel Reduction ◽  
Open Questions ◽  
Performance Computing

We investigate the usefulness of gossip-based reduction algorithms in a high-performance computing (HPC) context. We compare them to state-of-the-art deterministic parallel reduction algorithms in terms of fault tolerance and resilience against silent data corruption (SDC) as well as in terms of performance and scalability. New gossip-based reduction algorithms are proposed, which significantly improve the state-of-the-art in terms of resilience against SDC. Moreover, a new gossip-inspired reduction algorithm is proposed, which promises a much more competitive runtime performance in an HPC context than classical gossip-based algorithms, in particular for low accuracy requirements.

Ultra-high-performance microscope objectives: the state of the art in design, manufacturing, and testing

2007 ◽  
Author(s):  
Thomas Sure ◽  
Lambert Danner ◽  
Peter Euteneuer ◽  
Gerhard Hoppen ◽  
Armin Pausch ◽  
...  
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
The State

Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication

2014 ◽  
Vol 24 (02) ◽  
pp. 1550019
Author(s):  
Osama Al-Khaleel ◽  
Zakaria Al-Qudah ◽  
Mohammad Al-Khaleel ◽  
Raed Bani-Hani ◽  
Christos Papachristou ◽  
...  
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
The State ◽  
Partial Product ◽  
Hardware Implementations ◽  
Array Multipliers ◽  
Decimal Multiplication ◽  
Multiplier Circuit

This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.

scholarly journals AutoFolio: An Automatically Configured Algorithm Selector (Extended Abstract)

2017 ◽  
Author(s):  
Marius Lindauer ◽  
Frank Hutter ◽  
Holger H. Hoos ◽  
Torsten Schaub
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
The State ◽  
Problem Instance ◽  
Algorithm Selection ◽  
Algorithm Configuration ◽  
Optimal Values ◽  
Art Performance ◽  
The One

Algorithm selection (AS) techniques -- which involve choosing from a set of algorithms the one expected to solve a given problem instance most efficiently -- have substantially improved the state of the art in solving many prominent AI problems, such as SAT, CSP, ASP, MAXSAT and QBF. Although several AS procedures have been introduced, not too surprisingly, none of them dominates all others across all AS scenarios. Furthermore, these procedures have parameters whose optimal values vary across AS scenarios. In this extended abstract of our 2015 JAIR article of the same title, we summarize AutoFolio, which uses an algorithm configuration procedure to automatically select an AS approach and optimize its parameters for a given AS scenario. AutoFolio allows researchers and practitioners across a broad range of applications to exploit the combined power of many different AS methods and to automatically construct high-performance algorithm selectors. We demonstrate that AutoFolio was able to produce new state-of-the-art algorithm selectors for 7 well-studied AS scenarios and matches state-of-the-art performance statistically on all other scenarios. Compared to the best single algorithm for each AS scenario, AutoFolio achieved average speedup factors between 1.3 and 15.4.

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