Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

2012 ◽  
Vol 134 (6) ◽  
Author(s):  
Man Prakash Gupta ◽  
Minki Cho ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Thermal Management ◽  
Power Distribution ◽  
Peak Temperature ◽  
Management Technique ◽  
Time Intervals ◽  
Regular Time ◽  
Overall Performance ◽  
On Chip ◽  
Many Core ◽  
Power Configuration

In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.

An Investigation of Power Migration Policies for Many-Core Processors to Manage On-Chip Thermal Profile

2011 ◽  
Author(s):  
Man Prakash Gupta ◽  
Minki Cho ◽  
Saibal Mukhopadhyay ◽  
Satish Kumar
Keyword(s):  
Thermal Management ◽  
Power Distribution ◽  
Finite Size ◽  
Peak Temperature ◽  
Finite Size Effect ◽  
Management Technique ◽  
Thermal Profile ◽  
Migration Policies ◽  
On Chip ◽  
Many Core

Transition from single core to multicore technology has brought daunting challenge for thermal management of microprocessor chips. The issue of power dissipation in next generation chip will be far more critical as further transition from multicore to many-core processors is soon to be expected. It is very important to obtain uniform on-chip thermal profile with low peak temperature for improved performance and reliability of many-core processors. In this paper, a proactive thermal management technique called ‘power multiplexing’ is explored for many-core processors. Power multiplexing involves redistribution of locations of power dissipating cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. A comparative study of these policies has been performed enlisting their limits and advantages from the thermal and implementation perspective considering important relevant parameters such as migration frequency. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy leads to 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Proximity of active cores or power configuration on chip is characterized by a parameter ‘proximity index’ which emerges as an important parameter to represent the spatial power distribution on a chip. Global coolest replace policy optimizes the power map on chip taking care of not only the proximity of active cores but also the finite-size effect of chip and the 3D system of electronic package leading to almost uniform thermal profile on chip with lower average temperature.

scholarly journals Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

2018 ◽  
Vol 51 (7-8) ◽  
pp. 235-242 ◽  
Author(s):  
Arulmurugan Azhaganantham ◽  
Murugesan Govindasamy
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Power Distribution ◽  
Large Scale ◽  
Heat Dissipation ◽  
Peak Temperature ◽  
Heating Event ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don’t cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called “hotspot.” The peak temperature on the hotspot is minimized by Genetic Algorithm–based don’t care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%–28% peak temperature reduction can be achieved.

scholarly journals NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm

2018 ◽  
Vol 6 (2) ◽  
pp. 105
Author(s):  
A. Kalimuthu ◽  
M. Karthikeyan
Keyword(s):  
Resource Sharing ◽  
Clustering Algorithms ◽  
Font Size ◽  
Core System ◽  
Mesh Structure ◽  
Low Area ◽  
Area Overhead ◽  
Overall Performance ◽  
On Chip ◽  
Many Core

<span style="font-size: 9pt; font-family: 'Times New Roman', serif;">A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique</span>

Applying Periodic Thermal Management on Hard Real-Time Systems to Minimize Peak Temperature

2018 ◽  
Vol 27 (13) ◽  
pp. 1850208 ◽  
Author(s):  
Long Cheng ◽  
Kai Huang ◽  
Gang Chen ◽  
Biao Hu ◽  
Zhuangyi Jiang ◽  
...  
Keyword(s):  
Closed Form ◽  
Real Time ◽  
Thermal Management ◽  
Peak Temperature ◽  
Real Time Systems ◽  
Event Stream ◽  
And Performance ◽  
On Chip ◽  
Hard Real Time ◽  
Time Systems

Due to growing power density, on-chip temperature increases rapidly, which has hampered the reliability and performance of modern real-time systems. This paper studies how to minimize the peak temperature of real-time systems under hard real-time constraints with periodic thermal management. A closed-form representation of the peak temperature for such a periodic scheme is derived to tackle this problem. Based on this closed form and the arrival curve model, one offline approach and one online approach are proposed to minimize the peak temperature for a given event stream. The offline one does thermal optimization in design phase and introduces negligible runtime overhead. The online one computes dynamic power-control schemes which are adaptive to actual event arrivals and execution states. We conduct experiments on a real single-core processor and compare our approaches to two existing works. The temperature results measured from a physical thermal sensor demonstrate that the achieved maximal and average temperature reductions are 5[Formula: see text]K and 2.6[Formula: see text]K, respectively.

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

scholarly journals Near-Optimal Thermal Monitoring Framework for Many-Core Systems-on-Chip

2015 ◽  
Vol 64 (11) ◽  
pp. 3197-3209 ◽  
Author(s):  
Juri Ranieri ◽  
Alessandro Vincenzi ◽  
Amina Chebira ◽  
David Atienza ◽  
Martin Vetterli
Keyword(s):  
Thermal Monitoring ◽  
Systems On Chip ◽  
Monitoring Framework ◽  
On Chip ◽  
Many Core

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

2013 ◽  
Author(s):  
Dexue Zhang ◽  
Xiaoyang Zeng ◽  
Zongyan Wang ◽  
Weike Wang ◽  
Xinhua Chen
Keyword(s):  
Networks On Chip ◽  
Virtual Platform ◽  
On Chip ◽  
Many Core
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