Experimental Analysis Model of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers

2010 ◽  
Vol 132 (2) ◽  
Author(s):  
Huy N. Phan ◽  
Dereje Agonafer
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Analysis Model ◽  
Thermoelectric Coolers ◽  
Active Cooling ◽  
3D Ics ◽  
Cooling Method ◽  
Memory Applications

Presently, stack dice are used widely as low-power memory applications because thermal management of 3D architecture such as high-power processors inherits many thermal challenges. Inadequate thermal management of three-dimensional integrated circuits (3D-ICs) leads to reduction in performance, reliability, and ultimately system catastrophic failure. Heat dissipation of 3D systems is highly nonuniform and nonunidirectional due to many factors such as power architectures, transistors packing density, and real estate available on the chip. In this study, the development of an experimental model of an active cooling method to cool a 25 W stack-dice to approximately 13°C utilizing a multidimensional configured thermoelectric will be presented.

Response Time Analysis of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers

2010 ◽  
Vol 7 (2) ◽  
pp. 73-78
Author(s):  
Huy N. Phan ◽  
Dereje Agonafer
Keyword(s):  
Response Time ◽  
Heat Dissipation ◽  
Response Time Analysis ◽  
Time Analysis ◽  
Thermoelectric Coolers ◽  
Active Cooling ◽  
Setup Costs ◽  
3D Ics ◽  
Cooling Method ◽  
Thermal Chamber

Heat dissipation of 3D-ICs systems is highly nonuniform and nonunidirectional due to many factors such as power architecture and transistor packing density available on the chip. In this study, the cooling response time analysis of an active cooling method to cool a 25 W stack-dice to approximately 13°C within 400 s utilizing multidimensional configured thermoelectric coolers will be presented. The results obtained from this study are beneficial not only to 3D-ICs with or without core hopping architecture cooling, but also to thermal cycling of ICs in general, utilizing thermoelectric modules to obtain rapid and precision ramping control and lower setup costs compared to a conventional thermal chamber.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

2011 ◽  
Author(s):  
Matthew Redmond ◽  
Kavin Manickaraj ◽  
Owen Sullivan ◽  
Satish Kumar
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Density ◽  
Hot Spot ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermoelectric Coolers ◽  
Vertical Coupling ◽  
Spot Cooling

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

2014 ◽  
Author(s):  
Hanju Oh ◽  
Yue Zhang ◽  
Li Zheng ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Thermal Gradient ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
3D Ic ◽  
Significant Challenge ◽  
3D Ics ◽  
Silicon Vias ◽  
First Time

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.

Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

2016 ◽  
Vol 138 (1) ◽  
Author(s):  
Thomas Brunschwiler ◽  
Arvind Sridhar ◽  
Chin Lee Ong ◽  
Gerd Schlottig
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
High Performance ◽  
Heat Dissipation ◽  
Hybrid Approach ◽  
Three Dimensional ◽  
Heat Removal ◽  
Back Side

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat Flux

2010 ◽  
Vol 132 (4) ◽  
Author(s):  
Yoon Jo Kim ◽  
Yogendra K. Joshi ◽  
Andrei G. Fedorov ◽  
Young-Joon Lee ◽  
Sung-Kyu Lim
Keyword(s):  
Integrated Circuits ◽  
Mass Flow Rate ◽  
Thermal Management ◽  
Mass Flow ◽  
Flow Rate ◽  
Single Phase ◽  
Hot Spot ◽  
Three Dimensional ◽  
Two Phase ◽  
Two Phase Cooling

It is now widely recognized that the three-dimensional (3D) system integration is a key enabling technology to achieve the performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D-stacked ICs, the interlayer microfluidic cooling scheme is adopted and analyzed in this study focusing on a single cooling layer performance. The effects of cooling mode (single-phase versus phase-change) and stack/layer geometry on thermal management performance are quantitatively analyzed, and implications on the through-silicon-via scaling and electrical interconnect congestion are discussed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that the large internal pressure and the pumping pressure drop are significant limiting factors, along with significant mass flow rate maldistribution due to the presence of hot-spots. Nevertheless, two-phase cooling using R123 and R245ca refrigerants yields superior performance to single-phase cooling for the hot-spot fluxes approaching ∼300 W/cm2. In general, a hybrid cooling scheme with a dedicated approach to the hot-spot thermal management should greatly improve the two-phase cooling system performance and reliability by enabling a cooling-load-matched thermal design and by suppressing the mass flow rate maldistribution within the cooling layer.

Development of Backside Buried Metal Layer Technology for 3D-ICs

2019 ◽  
Vol 2019 (1) ◽  
pp. 000268-000273
Author(s):  
Naoya Watanabe ◽  
Yuuki Araga ◽  
Haruo Shimamoto ◽  
Katsuya Kikuchi ◽  
Makoto Nagata
Keyword(s):  
Integrated Circuits ◽  
Metal Layer ◽  
Three Dimensional ◽  
Chip Thickness ◽  
Power Delivery ◽  
Silicon Structure ◽  
Metal Insulator ◽  
3D Ics ◽  
Power Delivery Network ◽  
Global Power

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

Ceramic-Based Planar Heat Pipe (Plate) for Passive Electronics Cooling

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000159-000165
Author(s):  
M. Wilson ◽  
H. Anderson ◽  
J. Fellows ◽  
C. Lewinsohn
Keyword(s):  
Integrated Circuits ◽  
Phase Change ◽  
Heat Dissipation ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Electronics Cooling ◽  
Ceramic Materials ◽  
Back Side ◽  
Dimensional Network ◽  
Internal Networks

Heat dissipation has become a major hurdle for the electronics industry, especially as higher performance integrated circuits are being developed for the power industry. Two of the primary hurdles in dissipating this heat are:The thermal contact resistance between the IC and the cooling device.The ability to effectively spread the heat, such that traditional cooling technologies can be effective.By selecting ceramic materials that are thermo-mechanically matched (CTE) to IC materials, the proposed heat plate can be directly bonded by typical solder or braze techniques to the back-side of the IC. This eliminates thermal resistances due to contact and thermal interface materials. Within these heat plates, a three dimensional network of gas channels and fluid wicks spread the high-flux heat loads from localized hot spots to the surrounding regions via phase change fluids and mass transport. Like traditional heat pipes, these heat plates operate at nearly uniform temperature due to the phase change. The internal networks provide for multidimensional heat and mass flow, increasing their dissipating capability. By using matched ceramic materials, and the inclusion of a heat plate, these primary hurdles for heat dissipation can be mitigated. The performance of prototypical planar heat plates will be presented.

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