Discussion: “High-Speed Performance of Tapered Roller Thrust Bearings With Various Lubricating Systems” (Naik, V. V., Keim, E. L., and Neifert, H. R., 1970, ASME J. Lubr. Technol., 92, pp. 97–101)

1970 ◽  
Vol 92 (1) ◽  
pp. 102-103
Author(s):  
H. Raich
1970 ◽  
Vol 92 (1) ◽  
pp. 97-101
Author(s):  
V. V. Naik ◽  
E. L. Keim ◽  
H. R. Neifert

Using high oil-flow rates, 6-in-bore tapered roller thrust bearings were operated in a speed range of 3600 fpm to 10800 fpm with loads up to 70,000 lb. Bearing operating temperature is considered to be the principal criterion of operation. The effect of lubricating systems, speed, load, oil-flow rates, lubricant viscosity, and oil-inlet temperature on the operating temperature is demonstrated. The test-rig results are generalized by means of dimensional analysis enabling the designer to predict operating temperature for various operating conditions of speed, load, oil-flow rates, and oil-inlet viscosity.


1976 ◽  
Vol 98 (1) ◽  
pp. 73-79 ◽  
Author(s):  
J. W. Capitao ◽  
R. S. Gregory ◽  
R. P. Whitford

A comparison of the high-speed performance characteristics of tilting-pad, self-equalizing type thrust bearings through two independent full-scale programs is reported. This paper presents experimental data on centrally pivoted, 6-pad, 267-mm (10 1/2-in.) and 304-mm (12-in.) O.D. bearings operating at shaft speeds up to 14000 rpm and bearing loads ranging up to 2.76 MPa (400 psi). Data presented demonstrate the effects of speed and loading on bearing power loss and metal temperatures. Included is a discussion of optimum oil supply flow rate based upon considerations of bearing pad temperatures and power loss values.


Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.


2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.


2021 ◽  
Vol 1045 (1) ◽  
pp. 012040
Author(s):  
Fahim Faisal ◽  
Mirza Muntasir Nishat ◽  
Sayka Afreen Mim ◽  
Hafsa Akter ◽  
Md. Rafid Kaysar Shagor
Keyword(s):  

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