Development of Analytical Model to a Temperature Distribution of a First Level Package With a Nonuniformly Powered Die

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan

Microprocessors continue to grow in capabilities, complexity, and performance. Microprocessors typically integrate functional components such as logic and level two cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly nonuniform, and the assumption of a uniform heat flux across the die surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work (Kaisare et al., 2005, “Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die,” InterPACK 2005, San Francisco, CA, Jul. 17–22) has been done, which includes numerical analysis and thermal based optimization of a typical package consisting of a nonuniformly powered die, heat spreader, thermal interface materials I and II, and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a nonuniformly powered die is carried out for the first time. The analytical model for two-layer bodies developed by Haji-Sheikh et al. (2003, “Steady-State Heat Conduction in Multi-Layer Bodies,” Int. J. Heat Mass Transfer, 46(13), pp. 2363–2379) is extended to this typical package, which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology is applied to solve the equations for various surfaces to calculate the maximum junction temperature for a given multilayer body. Finally validation of the analytical solution is carried out using previously developed numerical model.

Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model.


Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.


Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.


2021 ◽  
Vol 11 (21) ◽  
pp. 10338
Author(s):  
Mohammed A. Hefni ◽  
Minghan Xu ◽  
Ferri Hassani ◽  
Seyed Ali Ghoreishi-Madiseh ◽  
Haitham M. Ahmed ◽  
...  

With the increasing engineering applications of geothermal borehole heat exchangers (BHEs), accurate and reliable mathematical models can help advance their thermal design and operations. In this study, an analytical model with a time-dependent heat flux boundary condition on the borehole wall is developed, capable of predicting the thermal performance of single, double, and multiple closed-loop BHEs, with an emphasis on solar- and waste-heat-assisted geothermal borehole systems (S-GBS and W-GBS) for energy storage. This analytical framework begins with a one-dimensional transient heat conduction problem subjected to a time-dependent heat flux for a single borehole. The single borehole scenario is then extended to multiple boreholes by exploiting lines of symmetry (or thermal superposition). A final expression of the temperature distribution along the center line is attained for single, double, and multiple boreholes, which is verified with a two-dimensional finite-element numerical model (less than 0.7% mean absolute deviation) and uses much lesser computational power and time. The analytical solution is also validated against a field-scale experiment from the literature regarding the borehole and ground temperatures at different time frames, with an absolute error below 6.3%. Further, the thermal performance of S-GBS and W-GBS is compared for a 3-by-3 borehole configuration using the analytical model to ensure its versatility in thermal energy storage. It is concluded that our proposed analytical framework can rapidly evaluate closed-loop geothermal BHEs, regardless of the numbers of boreholes and the type of the heat flux on the borehole wall.


Author(s):  
Rama R. Goruganthu ◽  
David Bethke ◽  
Shawn McBride ◽  
Tom Crawford ◽  
Jonathan Frank ◽  
...  

Abstract Spray cooling is implemented on an engineering tool for Time Resolved Emission measurements using a silicon solid immersion lens to achieve high spatial resolution and for probing high heat flux devices. Thermal performance is characterized using a thermal test vehicle consisting of a 4x3 array of cells each with a heater element and a thermal diode to monitor the temperature within the cell. The flip-chip packaged TTV is operated to achieve uniform heat flux across the die. The temperature distribution across the die is measured on the 4x3 grid of the die for various heat loads up to 180 W with corresponding heat flux of 204 W/cm2. Using water as coolant the maximum temperature differential across the die was about 30 °C while keeping the maximum junction temperature below 95 °C and at a heat flux of 200 W/cm2. Details of the thermal performance of spray cooling system as a function of flow rate, coolant


Aerospace ◽  
2021 ◽  
Vol 8 (6) ◽  
pp. 150
Author(s):  
Yeon-Kyu Park ◽  
Geuk-Nam Kim ◽  
Sang-Young Park

The CANYVAL-C (CubeSat Astronomy by NASA and Yonsei using a virtual telescope alignment for coronagraph) is a space science demonstration mission that involves taking several images of the solar corona with two CubeSats—1U CubeSat (Timon) and 2U CubeSat (Pumbaa)—in formation flying. In this study, we developed and evaluated structural and thermal designs of the CubeSats Timon and Pumbaa through finite element analyses, considering the nonlinearity effects of the nylon wire of the deployable solar panels installed in Pumbaa. On-orbit thermal analyses were performed with an accurate analytical model for a visible camera on Timon and a micro propulsion system on Pumbaa, which has a narrow operating temperature range. Finally, the analytical models were correlated for enhancing the reliability of the numerical analysis. The test results indicated that the CubeSats are structurally safe with respect to the launch environment and can activate each component under the space thermal environment. The natural frequency of the nylon wire for the deployable solar panels was found to increase significantly as the wire was tightened strongly. The conditions of the thermal vacuum and cycling testing were implemented in the thermal analytical model, which reduced the differences between the analysis and testing.


2014 ◽  
Vol 6 (2) ◽  
pp. 77-85
Author(s):  
Pratibha Joshi ◽  
Manoj Kumar

Many studies have been done previously on temperature distribution in inhomogeneous composite systems with perfect interface, having no discontinuities along it. In this paper we have determined steady state temperature distribution in two inhomogeneous composite systems with imperfect interface, having discontinuities in temperature and heat flux using decomposed immersed interface method and performed the numerical simulation on MATLAB.


2011 ◽  
Vol 52-54 ◽  
pp. 1411-1414 ◽  
Author(s):  
Bo Chen

Thermal design and analysis of a satellite borne FPGA is described in this paper. Thermal-conductive glue, vias and an aluminum bar were used to the FPGA and the PCB under the FPGA in order to help conduct the heat of the FPGA to heat sink. The results of finite element analysis showed that the case temperature of the FPGA decreased from 132.5°C to 55.4°C and the junction temperature decreased from 136.1°C to59.0 °C after the thermal design, which matches the requirements of thermal design.


2021 ◽  
pp. 153319
Author(s):  
Xiaoping Li ◽  
Hongyu Fan ◽  
Weifeng Liu ◽  
Yunqiu Cui ◽  
Chunjie Niu ◽  
...  

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