Effect of Chip and Pad Geometry on Solder Joint Formation in SMT

1993 ◽  
Vol 115 (4) ◽  
pp. 433-439 ◽  
Author(s):  
S. M. Heinrich ◽  
P. E. Liedtke ◽  
N. J. Nigro ◽  
A. F. Elkouh ◽  
P. S. Lee
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Integrated Approach ◽  
Contact Angles ◽  
Circuit Board ◽  
Zero Gravity ◽  
Cross Sectional ◽  
Board Density ◽  
Joint Formation ◽  
Maximum Utility

An analytical model of solder joint formation during a surface mount reflow process is developed for two-dimensional fillets whose flow may be restricted due to “finite” metallizations on a leadless component and the printed circuit board. Although these height and length constraints on the fillet geometry may result in obtuse contact angles, the solution is obtained in the form of an explicit integral, similar to that previously derived by the authors for the case of acute contact angles. This solution may also be recast into the form of elliptic integrals of the first and second kinds, thereby permitting one to evaluate the fillet geometry using mathematical tables or special function software, if desired, rather than resorting to a computer-based numerical quadrature. In addition an approximate zero-gravity solution is given by means of simple closed-form expressions relating the height, length, contact angles, and cross-sectional area of the fillet. Numerical results generated by implementing the “exact” integral solution for the joint profile are given in the form of dimensionless plots, relating fillet geometry to the solder properties (surface tension and density), amount of solder, chip height, and pad length. Also presented in dimensionless form are the approximate results from the zero-gravity model, which are independent of solder properties, yet are of sufficient accuracy for “small” joints. Because of their dimensionless nature, the results of the present paper may be of maximum utility to process engineers aiming to achieve desired joint geometries (e.g., to maximize fatigue life or to eliminate bridging problems), or to board designers responsible for selecting efficient footprint patterns to maximize board density. Models of solder joint formation, such as the one presented here, may be of most value when used in conjunction with stress analysis packages (e.g., finite element programs) and appropriate fatigue models. In this way an integrated approach to the design of solder joints and circuit boards may be taken, resulting in improved product reliability and performance.

Solder Joint Formation in Surface Mount Technology—Part I: Analysis

1990 ◽  
Vol 112 (3) ◽  
pp. 210-218 ◽  
Author(s):  
S. M. Heinrich ◽  
A. F. Elkouh ◽  
N. J. Nigro ◽  
Ping S. Lee
Keyword(s):  
Solder Joint ◽  
Laboratory Data ◽  
Integral Form ◽  
Contact Angles ◽  
Reflow Process ◽  
Cross Sectional ◽  
Joint Formation ◽  
Surface Mount ◽  
Theoretical Predictions ◽  
Joint Shape

An analytical model of solder joint formation during a surface mount reflow process is developed in the present paper, and the solution is obtained in an explicit integral form. For two limiting cases—infinitesimal and infinite solder areas—the solution is expressed in closed form. Numerical results illustrate the influence of the process parameters (surface tension, density, and cross-sectional area of the molten solder, and the contact angles between the solder andpretinning) on joint shape and overall fillet dimensions. Comparisons between theoretical predictions and laboratory data show excellent agreement.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Analysis of 16 QFN Device I/O Pads for Solderability Failures

2015 ◽  
Vol 2015 (1) ◽  
pp. 000675-000684
Author(s):  
Rama Hegde ◽  
Anne Anderson ◽  
Sam Subramanian ◽  
Andrew Mawer ◽  
Ed Hall ◽  
...  
Keyword(s):  
Cross Section ◽  
Printed Circuit Board ◽  
Depth Profiling ◽  
Lessons Learned ◽  
Circuit Board ◽  
Physical Analysis ◽  
Lead Frame ◽  
Cross Sectional ◽  
Root Cause ◽  
Industry Standard

In-process failures were experienced during printed circuit board (PCB) SMT assembly of a 16 Quad Flat No Leads (QFN) device. The failures appeared to be solderability related with QFN unit I/O pads not soldering robustly and sometimes leading to QFN detachment following board mounting. When assembly did take place on affected QFN units, the resulting solder joint was observed to be weak. This paper reports on very systematic analyses of the QFN device I/O pads using optical inspections, AES surface, AES depth profiling, SEM/EDX, SIMS, FIB and TEM cross-sectional measurements to determine the root cause of the failure and the failure mechanism. The detached QFN units, suspect and good unsoldered units, passing and failing units obtained from customers were examined. The industry standard surface mount solderability testing was performed on good and suspect parts, and all were observed to pass as evidenced by >95% coverage of the I/O pads. Optical inspections and a wide variety of physical analysis of the pads on fresh parts showed no anomalies with only the expected Au over Pd over Ni found. AES analysis was performed including depth profiling to look for any issues in the NiPdAu over base Cu plating layers that could be contributing the solderability failures. The AES depth profiling indicated AuPd film on the Ni under layer for the I/O pads as expected. No unexpected elements or oxide layers were observed at any layer. Then, one failing and one passing units were compared by doing FIB cross-section, FIB planar section and TEM cross-section analysis. The cross-sectional analysis showed rough Ni surface for the failing units, while the Ni surface was relatively smooth for the passing unit. Further, finer Cu grains and Ni grains were observed on the passing units. Additionally, the lead frame fabrication process mapping showed rough Cu, Ni “texturing” and use of low electro chemical polishing (ECP) current on the bad units compared to that of the good units. All affected bad units were confirmed coming from a second source Cu supplier with the rough Cu. The weak and irregular NiSn IMC formation on the bad units caused IMC separation and possible spalling during board solder reflow primarily due to the rough base Cu and irregular grain sizes and resulting lower ECP lead frame plating current. A possible final factor was marginally low Pd thickness. In conclusion, the 16 QFN device solderability failure root cause summary and the lessons learned from a wide variety of analysis techniques will be discussed.

Solder Joint Formation in Surface Mount Technology—Part II: Design

1990 ◽  
Vol 112 (3) ◽  
pp. 219-222 ◽  
Author(s):  
S. M. Heinrich ◽  
N. J. Nigro ◽  
A. F. Elkouh ◽  
P. S. Lee
Keyword(s):  
Surface Tension ◽  
Solder Joint ◽  
Solder Joints ◽  
Cross Sectional Area ◽  
Surface Mount Technology ◽  
Sectional Area ◽  
Cross Sectional ◽  
Joint Formation ◽  
Surface Mount ◽  
Surface Tension Model

In this paper dimensionless design curves relating fillet height and length to joint cross-sectional area are presented for surface-mount solder joints. Based on an analytical surface tension model, the advantage of these dimensionless curves is that they may be used for arbitrary values of solder density and surface tension. The range of applicability of previously developed approximate formulae for predicting joint dimensions is also investigated. A simple example problem is included to illustrate the use of both the design curves and the approximate formulae.

Solder joint defect classification based on ensemble learning

2017 ◽  
Vol 29 (3) ◽  
pp. 164-170 ◽  
Author(s):  
Hao Wu
Keyword(s):  
Random Forest ◽  
Solder Joint ◽  
Decision Trees ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
High Accuracy ◽  
Ensemble Method ◽  
Circuit Board ◽  
Content Type

Purpose This paper aims to inspect the defects of solder joints of printed circuit board in real-time production line, simple computing and high accuracy are primary consideration factors for feature extraction and classification algorithm. Design/methodology/approach In this study, the author presents an ensemble method for the classification of solder joint defects. The new method is based on extracting the color and geometry features after solder image acquisition and using decision trees to guarantee the algorithm’s running executive efficiency. To improve algorithm accuracy, the author proposes an ensemble method of random forest which combined several trees for the classification of solder joints. Findings The proposed method has been tested using 280 samples of solder joints, including good and various defect types, for experiments. The results show that the proposed method has a high accuracy. Originality/value The author extracted the color and geometry features and used decision trees to guarantee the algorithm's running executive efficiency. To improve the algorithm accuracy, the author proposes using an ensemble method of random forest which combined several trees for the classification of solder joints. The results show that the proposed method has a high accuracy.

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