Damage Initiation and Propagation in Voided Joints: Modeling and Experiment

2008 ◽  
Vol 130 (1) ◽  
Author(s):  
Leila Jannesari Ladani ◽  
Abhijit Dasgupta

This study examines damage initiation and propagation in solder joints with voids, under thermomechanical cyclic loading. An accelerated thermal cycling test is conducted on printed wiring assemblies (PWAs) containing 256 input/output (I/O) plastic ball grid arrays (PBGAs) with voided solder joints. Destructive and nondestructive failure analyses of the solder balls are used to detect the presence of voids and to relate the extent of damage propagation to the number of thermal cycles. Particular cases of voided and damaged joints are selected from these tests, to guide the development of a strategy for modeling damage propagation, using a three dimensional global-local finite element analysis (FEA). The displacement results of the global FEA at the top and bottom of the selected solder balls are used as the boundary conditions in a local FEA model, which focuses on the details of damage initiation and propagation in the individual solder ball. The local model is error seeded with voids based on cases selected in experiment. The damage propagation rate is monitored for all the cases. The technique used to quantify cyclic creep-fatigue damage is a continuum model based on energy partitioning. A method of successive initiation is used to model the growth and propagation of damage in the selected case studies. The modeling approach is qualitatively verified using the results of the accelerated thermal cycling test. The verified modeling technique described above is then used for parametric study of the durability of voided solder balls in a ChipArray Thin Core BGA with 132 I/O (CTBGA132) assemblies, under thermal cycling. The critical solder ball in the package is selected and is error seeded with voids with different sizes and various distances from damage initiation site. The results show that voids in general are not detrimental to thermal cycling durability of the CTBGA132 assembly, except when a large portion of the damage propagation path is covered with voids. Small voids can arrest the damage propagation, but generally do not provide a significant increase in durability because the damage zone deflects around the void and also continues to propagate from other critical regions in the solder ball.

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000224-000232 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  

Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.


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