Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

1998 ◽  
Vol 120 (1) ◽  
pp. 30-36 ◽  
Author(s):  
M. Asheghi ◽  
M. N. Touzelbaev ◽  
K. E. Goodson ◽  
Y. K. Leung ◽  
S. S. Wong
Keyword(s):  
Thermal Conductivity ◽  
Phonon Scattering ◽  
Single Crystal Silicon ◽  
Phonon Transport ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
A Value ◽  
Thermal Simulations ◽  
Silicon Device ◽  
Soi Substrates

Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, ds, to a value nearly 40 percent less than that of bulk silicon for ds = 0.42 μm. The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

Thermal Conductivity of Ultra Thin Single Crystal Silicon Layers: Part II — Experimental Data and Modeling at High Temperatures

2004 ◽  
Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi ◽  
K. E. Goodson
Keyword(s):  
Experimental Data ◽  
Thermal Conductivity ◽  
Single Crystal ◽  
High Temperatures ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Boltzmann Transport ◽  
Crystal Silicon ◽  
Strained Si

Simulations of the temperature field in Silicon-on-Insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This work presents the first experimental data for 20 and 100 nm thick single crystal silicon layers at high temperatures and develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to temperatures range 300–1000 K for silicon layer thicknesses from 10 nm to 1 μm (and even bulk) and agrees well with the experimental data. In addition, the model has an excellent agreement with the predictions of thin film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation, although it is significantly more robust and convenient for integration into device simulators. The experimental data and predictions are required for accurate thermal simulation of the semiconductor devices, nanostructures and in particular the SOI and strained-Si transistors.

From the Casimir Limit to Phononic Crystals: 20 Years of Phonon Transport Studies Using Silicon-on-Insulator Technology

2013 ◽  
Vol 135 (6) ◽  
Author(s):  
Amy M. Marconnet ◽  
Mehdi Asheghi ◽  
Kenneth E. Goodson
Keyword(s):  
Room Temperature ◽  
Crystalline Silicon ◽  
Phonon Dispersion ◽  
Single Crystal Silicon ◽  
Phonon Transport ◽  
Silicon On Insulator ◽  
Boundary Scattering ◽  
Porous Films ◽  
Crystal Silicon ◽  
20 Nm

Silicon-on-insulator (SOI) technology has sparked advances in semiconductor and MEMs manufacturing and revolutionized our ability to study phonon transport phenomena by providing single-crystal silicon layers with thickness down to a few tens of nanometers. These nearly perfect crystalline silicon layers are an ideal platform for studying ballistic phonon transport and the coupling of boundary scattering with other mechanisms, including impurities and periodic pores. Early studies showed clear evidence of the size effect on thermal conduction due to phonon boundary scattering in films down to 20 nm thick and provided the first compelling room temperature evidence for the Casimir limit at room temperature. More recent studies on ultrathin films and periodically porous thin films are exploring the possibility of phonon dispersion modifications in confined geometries and porous films.

Thermal Conductivity Measurements of Ultra-Thin Single Crystal Silicon Layers

2005 ◽  
Vol 128 (1) ◽  
pp. 75-83 ◽  
Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Single Crystal ◽  
Data Storage ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Thermal Engineering ◽  
Boltzmann Transport ◽  
Crystal Silicon ◽  
Strained Si

Self-heating in deep submicron transistors (e.g., silicon-on-insulator and strained-Si) and thermal engineering of many nanoscale devices such as nanocalorimeters and high-density thermomechanical data storage are strongly influenced by thermal conduction in ultra-thin silicon layers. The lateral thermal conductivity of single-crystal silicon layers of thicknesses 20 and 100nm at temperatures between 30 and 450K are measured using joule heating and electrical-resistance thermometry in suspended microfabricated structures. In general, a large reduction in thermal conductivity resulting from phonon-boundary scattering is observed. Thermal conductivity of the 20nm thick silicon layer at room temperature is nearly 22Wm−1K−1, compared to the bulk value, 148Wm−1K−1. The predictions of the classical thermal conductivity theory that accounts for the reduced phonon mean free paths based on a solution of the Boltzmann transport equation along a layer agrees well with the experimental results.

In-plane Thermal Conductivity Determination in Silicon on Insulator (SOI) Structures Through Thermoreflectance Measurements

2010 ◽  
Vol 1267 ◽  
Author(s):  
Max S Aubain ◽  
Prabhakar Bandaru
Keyword(s):  
Thermal Conductivity ◽  
Heat Dissipation ◽  
Numerical Solutions ◽  
Thin Layers ◽  
Silicon On Insulator ◽  
Device Layer ◽  
Multiphysics Modeling ◽  
Modeling Software ◽  
Silicon Device ◽  
Soi Substrates

AbstractHeat dissipation in Silicon-On-Insulator (SOI) based microdevices is hindered in the silicon device layer by the low thermal conductivity of the neighboring oxide and reduced in-plane thermal conductivity in very thin layers. This work shows that the in-plane thermal conductivity of a 260 nm thick device layers in SOI substrates can be characterized by measuring the temperature distributions induced by AC joule heating through microfabricated heaters by a scanning thermoreflectance technique. These data were fitted to numerical solutions of the heat conduction equation calculated using COMSOL® Multiphysics modeling software, suggesting the in-plane thermal conductivity of the device layer is reduced to 90±10 W/(m.K), which is consistent with phonon boundary scattering theory predictions.

Thermal Conductivity of Ultra Thin Single Crystal Silicon Layers: Part I — Experimental Measurements at Room and Cryogenic Temperatures

2004 ◽  
Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Single Crystal ◽  
Data Storage ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Thermal Engineering ◽  
Boltzmann Transport ◽  
Crystal Silicon ◽  
Strained Si

Self-heating in deep submicron transistors (e.g., Silicon-on-insulator and strained-Si) and thermal engineering of many nanoscale devices such as nanocalorimeters and high-density thermomechanical data storage are strongly influenced by thermal conduction in ultra-thin silicon layers. The lateral thermal conductivity of single-crystal silicon layers of thicknesses 20 and 100 nm at temperatures between 30 and 300 K was measured using Joule heating and electrical-resistance thermometry in suspended microfabricated structures. In general, a large reduction in thermal conductivity resulting from phonon-boundary scattering, particularly at low temperatures, is observed. Thermal conductivity of the 20 nm thick silicon layer at room temperature is nearly 22 W m−1K−1, compared to the bulk value, 148 W m−1K−1. The predictions of the classical thermal conductivity theory that accounts for the reduced phonon mean free paths based on a solution of the Boltzmann transport equation along a layer agrees well with the experimental results.

Mean Free Path Effects on the Experimentally Measured Thermal Conductivity of Single-Crystal Silicon Microbridges

2013 ◽  
Vol 135 (9) ◽  
Author(s):  
Timothy S. English ◽  
Leslie M. Phinney ◽  
Patrick E. Hopkins ◽  
Justin R. Serrano
Keyword(s):  
Thermal Conductivity ◽  
Single Crystal ◽  
Microelectromechanical Systems ◽  
Single Crystal Silicon ◽  
Operating Conditions ◽  
Silicon On Insulator ◽  
Beam Diameter ◽  
Boltzmann Transport ◽  
Crystal Silicon ◽  
Thermal Conductivities

Accurate thermal conductivity values are essential for the successful modeling, design, and thermal management of microelectromechanical systems (MEMS) and devices. However, the experimental technique best suited to measure the thermal conductivity of these systems, as well as the thermal conductivity itself, varies with the device materials, fabrication processes, geometry, and operating conditions. In this study, the thermal conductivities of boron doped single-crystal silicon microbridges fabricated using silicon-on-insulator (SOI) wafers are measured over the temperature range from 80 to 350 K. The microbridges are 4.6 mm long, 125 μm tall, and either 50 or 85 μm wide. Measurements on the 85 μm wide microbridges are made using both steady-state electrical resistance thermometry (SSERT) and optical time-domain thermoreflectance (TDTR). A thermal conductivity of 77 Wm−1 K−1 is measured for both microbridge widths at room temperature, where the results of both experimental techniques agree. However, increasing discrepancies between the thermal conductivities measured by each technique are found with decreasing temperatures below 300 K. The reduction in thermal conductivity measured by TDTR is primarily attributed to a ballistic thermal resistance contributed by phonons with mean free paths larger than the TDTR pump beam diameter. Boltzmann transport equation (BTE) modeling under the relaxation time approximation (RTA) is used to investigate the discrepancies and emphasizes the role of different interaction volumes in explaining the underprediction of TDTR measurements.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

scholarly journals A Flexible PI/Si/SiO2 Piezoresistive Microcantilever for Trace-Level Detection of Aflatoxin B1

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu
Keyword(s):  
Single Crystal ◽  
Aflatoxin B1 ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Wheatstone Bridge ◽  
Silicon On Insulator ◽  
Passivation Layer ◽  
Spring Constant ◽  
Trace Level ◽  
Crystal Silicon

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.

scholarly journals Анодное окисление слоев кремний-на-изоляторе, созданных методом водородного переноса

2019 ◽  
Vol 53 (2) ◽  
pp. 253
Author(s):  
И.Е. Тысченко ◽  
И.В. Попов ◽  
Е.В. Спесивцев
Keyword(s):  
Oxidation Rate ◽  
Hydrogen Transfer ◽  
Single Crystal Silicon ◽  
Interatomic Interaction ◽  
Surface Region ◽  
Bound State ◽  
Silicon On Insulator ◽  
Bulk Single Crystal ◽  
Crystal Silicon ◽  
Insulator Layer

AbstractThe anodic oxidation rate of silicon-on-insulator films fabricated by hydrogen transfer is studied as a function of the temperature of subsequent annealing. It is established that the oxidation rate of transferred silicon-on-insulator films is five times lower compared to the oxidation rate of bulk single-crystal silicon samples. The oxidation rate increases, as the annealing temperature is elevated in the range 700–1100°C and as the depth of gradually removed anode-oxidized layers is increased. The results obtained in the study are attributed to an increase in the efficiencies of the anodic current and oxygen–silicon interatomic interaction due to the annealing of defects and due to release of hydrogen from the bound state, respectively. The formation of hydrogen bubbles in the surface region of silicon due to the diffusion of hydrogen, released in the process of the oxidation reaction, towards micropores in the silicon-on-insulator layer is detected.

Transfer of an ultrathin single crystal silicon film from a Silicon On Insulator to a polymer

2020 ◽  
pp. 100107
Author(s):  
L.G. Michaud ◽  
E. Azrak ◽  
C. Castan ◽  
F. Fournel ◽  
F. Rieutord ◽  
...  
Keyword(s):  
Single Crystal ◽  
Silicon Film ◽  
Single Crystal Silicon ◽  
Silicon On Insulator ◽  
Crystal Silicon
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