Effect of RCC on the Reliability of Adhesive Flip Chip Joints

2006 ◽  
Vol 129 (3) ◽  
pp. 260-265 ◽  
Author(s):  
Laura K. Frisk ◽  
Kati H. Kokko
Keyword(s):  
Flip Chip ◽  
Printed Circuit Boards ◽  
Coefficient Of Thermal Expansion ◽  
Temperature Cycling ◽  
Circuit Boards ◽  
Adhesive Film ◽  
The Difference ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Conductive Particles

A need for higher packaging density and functionality has increased the use of new packaging technologies, which has also caused demand for higher interconnect densities on printed circuit boards (PCBs). Sequential build-up (SBU) processes can be used to meet these demands. In the SBU process, additional dielectric and conductor layers are formed on a core board, which is typically made of FR-4. Microvias are formed on these layers to achieve an electrical connection between them and the core board. Resin-coated copper foil (RCC) is the most widely used dielectric layer in the SBU process. The effect of RCC on the reliability of flip chip joints with anisotropically conductive adhesive film (ACF) was studied. Two substrates were used. The difference between the substrates was RCC laminated on the other substrate. The reliability of the test samples was studied using a temperature cycling test and a constant humidity test. The reliability of the substrate with the RCC was found to be better in both tests. Failure mechanisms were studied after the tests, using optical and scanning electron microscopes. After the temperature cycling, several of the test samples made with two highest bonding pressures showed delamination, which has probably caused the failures. In addition, failures occurred during the changes in the test temperature. These were probably caused by warping of the flip chip package. No delamination was found in the test samples with the lowest pressure. The failures in these series were probably caused by relaxation of the adhesive matrix and by too low deformation of the conductive particles. Several cracks had formed on the FR-4 substrates without the RCC during the temperature cycling. In addition, air bubbles were found in the test samples with the FR-4 substrates without the RCC. Since RCC is a pure resin system, it has a high coefficient of thermal expansion, which may cause problems, especially when large components are attached to it. However, in this study, the RCC was found to increase the reliability of the flip chip joints made with ACF during both temperature cycling and constant humidity testing.

Advanced Build-up Materials for High Speed Transmission Application

2018 ◽  
Vol 2018 (1) ◽  
pp. 000305-000309 ◽  
Author(s):  
Shiro Tatsumi ◽  
Shohei Fujishima ◽  
Hiroyuki Sakauchi
Keyword(s):  
High Speed ◽  
Printed Circuit Boards ◽  
Transmission Loss ◽  
Coefficient Of Thermal Expansion ◽  
Strip Line ◽  
Circuit Boards ◽  
Additive Process ◽  
Printed Circuit ◽  
Low Dielectric ◽  
Transmission Speed

Abstract Build-up process is a highly effective method for miniaturization and high density integration of printed circuit boards. Along with increasing demands for high transmission speed of electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to reduce the transmission loss. Our insulation materials are used in a semi-additive process (SAP) with low dielectric loss tangent, smooth resin surface after desmear, and good insulation reliability. Actually, the transmission loss of strip line substrates and Cu surface roughness impact on transmission loss were measured using our materials. Furthermore, low dielectric molding film with low coefficient of thermal expansion (CTE) and low Young's modulus are introduced.

Advanced Build-up Materials and Processes for Packages with Fine Line and Space

2014 ◽  
Vol 2014 (1) ◽  
pp. 000444-000447 ◽  
Author(s):  
Yoshio Nishimura ◽  
Hirohisa Narahashi ◽  
Shigeo Nakamura ◽  
Tadahiko Yokota
Keyword(s):  
Printed Circuit Boards ◽  
Coefficient Of Thermal Expansion ◽  
High Reliability ◽  
Electronic Devices ◽  
Circuit Boards ◽  
Additive Process ◽  
Fine Line ◽  
Printed Circuit ◽  
Low Dielectric ◽  
Line Space

Printed circuit boards manufactured by a semi-additive process are widely used for packaging substrates. Along with increasing demands of downsizing electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to be miniaturized with high density of circuit wirings. We report our insulation build-up materials and processes for advanced packages with fine line/space and high reliability. The insulation materials we developed show low coefficient of thermal expansion (CTE), low dielectric loss tangent and good thinner insulation reliability. They can produce fine line and space (FLS) under 10μm pitch by a semi-additive process.

scholarly journals Reduced-Reflection Multilayer PCB Microstrip with Discontinuity Characterization

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1473
Author(s):  
Aleksandr Vasjanov ◽  
Vaidotas Barzdenas
Keyword(s):  
Printed Circuit Boards ◽  
Dielectric Material ◽  
Academic Research ◽  
System Level ◽  
Reference Plane ◽  
Impedance Change ◽  
Circuit Boards ◽  
Impedance Mismatch ◽  
The Difference ◽  
Technology And Communication

In the era of technology and communication, printed circuit boards (PCBs) can be found in a myriad of devices—from ordinary household items, to state of the art custom metrology equipment. Different types of component for wireless communications are available and come in various packages, supplied by multiple manufacturers. The signal landpads for some high-frequency connectors and components, encapsulated in larger packages, are usually wider than the controlled impedance trace, thereby introducing unwanted impedance mismatch and resulting in signal reflections. The component land pad and microstrip width a discrepancy issue can be found in both complex high-density industrial devices and system-level academic research papers. This paper addresses the topic of compensating discontinuities, introduced by signal pads, which are wider than the target impedance microstrip, characterizes the difference between the compensated and uncompensated microstrip with discontinuity, and proposes a generalized guideline on compensating for the introduced impedance change in multilayer PCBs. The compensation method is based upon carefully designing the stackup of the PCB allowing for a reference plane cutout under the discontinuity to even out the impedance mismatch. A 6-layer PCB with IT180A dielectric material containing three structures has been manufactured and characterized using an Agilent E8363B vector network analyzer (VNA). A 4–12 dB improvement in S11 response in the whole frequency range up to 10 GHz, compared to that when no compensation has been applied, was observed.

Fast Precise Positioning of Circular Mark in Automatic Optical Inspection

2013 ◽  
Vol 325-326 ◽  
pp. 1614-1618
Author(s):  
Guang Jie Xiong ◽  
Yu Fei Liu ◽  
Rui Zhen Liu
Keyword(s):  
Printed Circuit Boards ◽  
Positioning Error ◽  
Circuit Boards ◽  
Precise Positioning ◽  
Automatic Optical Inspection ◽  
Running Time ◽  
Printed Circuit ◽  
Optical Inspection ◽  
Positioning Method ◽  
The Difference

Captured circular marks are deformed sometimes when Automatic Optical Inspection (AOI) is used to detect various defects on Printed Circuit Boards (PCB), which may affect the precision of inspection. A new accurate positioning method of circular marks is proposed to solve the problem by obtaining the center of the most round ellipse based on the criterion that the ratio of the difference between the length and width of its circumscribed rectangle and the width of the rectangle is less than 0.1. The simulation tests show that, if the mark has much more deformations, the center positioning error of the proposed algorithm is about 0.013 pixels, and the running time is less than 40ms. Therefore, the proposed method provides good characteristics such as speediness, strong anti-interference ability and robustness.

scholarly journals Assembly of Cu Wirings with Ultrasmooth and High-Adhesive Electroless Cu Seed Layer by Using UV Modification and Low Attenuation of High-Frequency Transmission Property

2020 ◽  
Vol 17 (2) ◽  
pp. 45-51
Author(s):  
Masaya Toba ◽  
Shuji Nomoto ◽  
Nobuhito Komuro ◽  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
...  
Keyword(s):  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Peel Strength ◽  
60 Ghz ◽  
Circuit Boards ◽  
Seed Formation ◽  
Anchoring Effect ◽  
Semiconductor Packages

Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ultrare-liable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by via formation by laser for dielectric, desmear, electroless Cu seed formation, photoresist patterning, electrolytic Cu plating, resist stripping, and seed layer etching. Although a desmear process can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of a desmear process, we applied a UV modification for the surface of dielectric to realize a smooth and high-adhesive seed layer against dielectric. We obtained .8 kN/m of peel strength between dielectric and Cu seed layer in spite of surface roughness of the dielectric being 45 nm by a nanolevel anchoring effect at the UV-modified layer. Because of the smooth interface by UV modification, the S21 value of microstrip line was 26% improved compared with that assembled through the desmear process at 60 GHz.

Analysis of Electron Channeling Contrast Imaging in Scanning Electron Microscopes

2018 ◽  
Vol 768 ◽  
pp. 52-58
Author(s):  
Zi Wei Liu ◽  
Chu Сheng Lin ◽  
Cai Fen Jiang ◽  
Jia Jie Hua ◽  
Ji Mei Zhang ◽  
...  
Keyword(s):  
Influence Factors ◽  
Sample Surface ◽  
Contrast Imaging ◽  
Material Microstructure ◽  
Electron Channeling ◽  
Channel Effect ◽  
The Difference ◽  
Electron Microscopes ◽  
Scanning Electron Microscopes ◽  
Scanning Electron

In the paper, the influence factors of electron channeling contrast imaging (ECCI) on crystalline material microstructure characterization by scanning electron microscopes (SEMs) were analyzed, such as electric current, accelerating voltage and sample material’s surface conditions. It was found that high current, appropriate accelerating voltage and smooth sample surface were more beneficial to obtaining an ideal channel effect pattern. In addition, the difference between the channel effect contrast and the EBSD technology was also investigated. And the results showed that the channel effect contrast image could qualitatively characterize grains with different orientations. However, it was far less sensitive than EBSD in characterizing small angle grain boundaries.

Mounting Leadless Chip Carriers onto Printed Circuit Boards

1982 ◽  
Vol 1 (1) ◽  
pp. 38-43 ◽  
Author(s):  
D. Fishman ◽  
N. Cooper
Keyword(s):  
Thermal Expansion ◽  
Thermal Cycling ◽  
Printed Circuit Boards ◽  
Coefficient Of Thermal Expansion ◽  
Cycling Performance ◽  
Circuit Board ◽  
Circuit Boards ◽  
Acceptable Solution ◽  
Printed Circuit ◽  
Chip Carrier

It is reasoned that wide penetration of chip carriers into equipment for professional and commercial applications depends on developing methods for mounting the leadless types directly on to conventional polymer type printed circuit boards. The main problem to be overcome is fatigue failure of the solder joints due to the mismatch in thermal expansion, evidenced by poor thermal cycling performance. In this paper the thermal cycling performance is compared when four sizes of ceramic leadless chip carrier are mounted on a selection of printed circuit board materials ranging from the conventional to those specially formulated, either on the basis of matching the coefficient of thermal expansion of the chip carrier material, or to provide a layer of compliant elastomer material underneath the layer bearing the copper contact layer, so that strain due to thermal expansion mismatch is not transmitted to the solder layer. Over 400 thermal cycles (−55 to + 125°C) were recorded using proprietary versions of elastomer coated substrates. For appropriate applications the basis is thus laid for an economic and technically acceptable solution. The practical implications of two methods of soldering—wave (jet) and vapour phase—are also discussed.

Process Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Packages

2001 ◽  
Vol 123 (4) ◽  
pp. 331-337 ◽  
Author(s):  
K. N. Chiang ◽  
C. W. Chang ◽  
C. T. Lin
Keyword(s):  
Tensile Stress ◽  
Process Modeling ◽  
Flip Chip ◽  
Thermal Loading ◽  
Conductive Adhesive ◽  
Adhesive Film ◽  
Anisotropic Conductive Adhesive ◽  
Fine Pitch ◽  
Assembly Technology ◽  
Conductive Particles

Development of flip-chip-on-glass (FCOG) assembly technology using anisotropic conductive adhesive/film (ACA/ACF) is currently underway to achieve fine pitch interconnections between driver IC and flat panel display. Conductive adhesives are characterized by fine-pitch capability and more environment compatibility. Anisotropic conductive adhesive/film (ACA/ACF) is composed of an adhesive resin and conductive particles, such as metallic or metal-coated polymer particles. In contrast to a solder type flip chip interconnection, the electric current passing through conductive particles becomes the dominant conduction paths. The interconnection between the particles and the conductive surfaces is constructed by the elastic/plastic deformation of conductive particles with contact pressure, which is maintained by tensile stress in the adhesive. Although loss of electric contact can occur when the adhesive expands or swells in the Z- axis direction, delamination and cracking can occur in the adhesive layer while the tensile stress is excessive. In addition to performing processing simulations as well as reliability modeling, this research investigates the contact force that is developed and relaxed within the interconnection during the process sequence by using nonlinear finite element simulations. Environmental effects, such as high temperature and thermal loading, are also discussed. Moreover, a parametric study is performed for process design. To improve performance and reliability, variables such as ACF materials, proper processing conditions are discussed as well. Furthermore, this study presents a novel method called equivalent spring method, capable of significantly reducing the analysis CPU time and make process modeling and contact analysis of the 3D ACA/ACF process possible.

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