Dynamics Of Board-Level Drop Impact

2004 ◽  
Vol 127 (3) ◽  
pp. 200-207 ◽  
Author(s):  
E. H. Wong

The dynamic response of the printed circuit board (PCB) in a standard board-level drop impact test has been modeled as a spring-mass system, a beam, and a plate. Analytical solutions for the time-response and amplification of the deflection, bending moment, and acceleration at any point on the PCB have been developed and validated with finite element analysis. The analyses have shown that (i) the response of the PCB was dominated by the fundamental mode and (ii) the response of the PCB depends heavily on the ratio between the frequency of the PCB and the input acceleration pulse. The bending moment on the PCB has been shown beyond doubt to be responsible for the interconnection stress; the maximum moment on the PCB can be most effectively reduced through reducing the PCB thickness. The rapid receding of the higher modes in the moment response suggests that it can be adequately and effectively modeled using the standard implicit time-integration code.

Author(s):  
Jefferson Talledo

Leadframe-based packages are commonly used for semiconductor power devices. With these packages, heat dissipation is much better compared with laminate substrated-based packages. However, the solder joint reliability requirement under thermal cycling condition is also higher and this is what makes the development of a power package challenging. One of the usual requirements from customers is that there should be no solder joint failure up to 2,000 thermal cycles. This paper presents the thermomechanical simulation of a power leadframe package that was conducted to improve its solder joint reliability. Board level solder joint cycle life was predicted using finite element analysis and the result was validated with actual solder life result from board level reliability evaluation. Since available solder prediction equation was for the characteristic life (63.2% accumulative failure), using the normalized characteristic life was implemented for predicting the number of cycles to first failure of the solder joint connection and the approach showed good agreement with the actual result. Results also indicated that the choice of epoxy mold material and the type of PCB (printed circuit board) have a significant contribution to the solder joint reliability performance.


2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.


2005 ◽  
Vol 127 (4) ◽  
pp. 496-502 ◽  
Author(s):  
E. H. Wong ◽  
Y-W Mai ◽  
S. K. W. Seah

A fundamental understanding of the dynamics of the PCB assembly when subjected to a half-sine acceleration has also been obtained through analyzing the PCB as a spring mass system, a beam, and a plate, respectively. The magnitude of stresses in solder interconnection due to flexing of the PCB is two orders higher than the magnitude of the stresses induced by acceleration and inertia loading the IC package. By ignoring the inertia loading, computational effort to evaluate the interconnection stresses due to PCB flexing can be reduced significantly via a two-step dynamic-static analysis. The dynamic analysis is first performed to evaluate the PCB bending moment adjacent the package, and is followed by a static analysis where the PCB bending moment is applied around the package. Parametric studies performed suggest a fundamental difference in designing for drop impact and designing for temperature cycling. The well-known design rules for temperature cycling—minimizing package length and maximizing interconnection standoff—does not work for drop impact. Instead, drop impact reliability can be enhanced by increasing the interconnection diameter, reducing the modulus of the interconnection materials, reducing the span of the PCB, or using either a very thin or a very thick PCB.


Author(s):  
S. K. W. Seah ◽  
E. H. Wong ◽  
R. Ranjan ◽  
C. T. Lim ◽  
Y.-W. Mai

This paper presents the results of experiments aimed at studying the effects of drop impact on portable electronics and reproducing these effects in controllable tests. Firstly, a series of drop tests were performed on consumer products (mobile phones and PDAs) to understand how the printed circuit board (PCB) within a product behaves in actual drop conditions. These product-level drop tests show that in drop impact, there are three possible types of mechanical response which can stress the 2nd level interconnections of CSP and BGA packages, namely: 1) flexing of the PCB on its supports, dominated by the 1st (fundamental) natural frequency; 2) flexing of the PCB resulting from direct impact or knocking against the PCB, typically dominated by higher natural frequencies; and 3) inertia loading on the solder joints due to high accelerations. Next, a series of board-level experiments were designed to separately study each of the three types of mechanical response. Board flexing due to direct impacts is the most severe response due to the strong strain amplitudes generated. Given the same input shock, the conventional board-level test — where the PCB flexes on its supports — produces much lower strain amplitudes. Inertia loading on the solder joints is practically negligible. Since PCB flexing is the main failure driver, a simple vibration test, which reproduces the strains observed in drop impact, is suggested as an alternative to time-consuming drop impact tests.


2007 ◽  
Vol 129 (3) ◽  
pp. 266-272 ◽  
Author(s):  
Fang Liu ◽  
Guang Meng ◽  
Mei Zhao

Dynamic properties of printed circuit board (PCB) assembly under drop impact are investigated when viscoelasticity of substrate materials is considered. The main materials of a PCB substrate are macromolecule resins, which are typical viscoelastic materials. From the viewpoint of viscoelasticity, the dynamics of PCBs under drop impact is analyzed based on mass-damping-spring, beam, and plate theories. It is demonstrated that the viscoelasticity of a PCB has distinct influences on the dynamic properties of PCBs under board-level drop impact. When there is an increase in the viscosity of substrate materials, the damping coefficients of PCBs would rise, its deflection and acceleration responses could diminish faster, and the maximum deflection of PCBs would become smaller. Meanwhile, with the same viscosity and drop impact conditions, a larger plate would produce a bigger deflection response. Therefore, drop impact reliability could be enhanced by choosing substrate material of larger viscoelasticity and reducing properly the size of PCBs. Dynamic analysis of PCBs under drop impact not only contributes to perfecting theoretical research, but also provides a reference for the choice of substrate materials and reliability design of PCBs when electronic products are devised.


Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.


2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.


2009 ◽  
Vol 419-420 ◽  
pp. 37-40
Author(s):  
Shiuh Chuan Her ◽  
Shien Chin Lan ◽  
Chun Yen Liu ◽  
Bo Ren Yao

Drop test is one of the common methods for determining the reliability of electronic products under actual transportation conditions. The aim of this study is to develop a reliable drop impact simulation technique. The test specimen of a printed circuit board is clamped at two edges on a test fixture and mounted on the drop test machine platform. The drop table is raised at the height of 50mm and dropped with free fall to impinge four half-spheres of Teflon. One accelerometer is mounted on the center of the specimen to measure the impact pulse. The commercial finite element software ANSYS/LS-DYNA is applied to compute the impact acceleration and dynamic strain on the test specimen during the drop impact. The finite element results are compared to the experimental measurement of acceleration with good correlation between simulation and drop testing. With the accurate simulation technique, one is capable of predicting the impact response and characterizing the failure mode prior to real reliability test.


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