Delay Performance under the Joint Scheduling over Gilbert-Elliot Channel

2006 ◽  
Author(s):  
Fumio Ishizaki ◽  
Gang Uk Hwang
Keyword(s):  
Delay Performance

Routing Optimization with Efficient Second Order Distributed Approach Using Congestion Control Rules

2017 ◽  
Vol 7 (7) ◽  
pp. 363
Author(s):  
Jaya Pratha Sebastiyar ◽  
Martin Sahayaraj Joseph
Keyword(s):  
Congestion Control ◽  
Second Order ◽  
Back Pressure ◽  
Order Method ◽  
Delay Performance ◽  
Routing Optimization ◽  
Distributed Approach ◽  
Control Rules ◽  
Primal Dual ◽  
Queue Stability

Distributed joint congestion control and routing optimization has received a significant amount of attention recently. To date, however, most of the existing schemes follow a key idea called the back-pressure algorithm. Despite having many salient features, the first-order sub gradient nature of the back-pressure based schemes results in slow convergence and poor delay performance. To overcome these limitations, the present study was made as first attempt at developing a second-order joint congestion control and routing optimization framework that offers utility-optimality, queue-stability, fast convergence, and low delay.  Contributions in this project are three-fold. The present study propose a new second-order joint congestion control and routing framework based on a primal-dual interior-point approach and established utility-optimality and queue-stability of the proposed second-order method. The results of present study showed that how to implement the proposed second-order method in a distributed fashion.

Delay performance in wireless multi-hop networks

2010 ◽  
Vol 30 (1) ◽  
pp. 134-136
Author(s):  
Ying LIN ◽  
Li XU
Keyword(s):  
Delay Performance

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Evaluating CRoS-NDN: a comparative performance analysis of a controller-based routing scheme for named-data networking

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
João Vitor Torres ◽  
Igor Drummond Alvarenga ◽  
Raouf Boutaba ◽  
Otto Carlos Muniz Bandeira Duarte
Keyword(s):  
Distribution Networks ◽  
Content Distribution Networks ◽  
Named Data Networking ◽  
Comparative Performance ◽  
Delay Performance ◽  
Data Packets ◽  
Routing Scheme ◽  
Wide Range ◽  
New Locations ◽  
Data Networking

Abstract The huge amount of content names available in Named-Data Networking (NDN) challenges both the required routing table size and the techniques for locating and forwarding information. Content copies and content mobility exacerbate the scalability challenge to reach content in the new locations. We present and analyze the performance of a proposed Controller-based Routing Scheme, named CRoS-NDN, which preserves NDN features using the same interest and data packets. CRoS-NDN supports content mobility and provides fast content recovery from copies that do not belong to the consumer-producer path because it splits identity from location without incurring FIB size explosion or supposing prefix aggregation. It provides features similar to Content Distribution Networks (CDN) in NDN, and improves the routing efficiency. We compare our proposal with similar routing protocols and derive analytical expressions for lower-bound efficiency and upper-bound latency. We also conduct extensive simulations to evaluate results in data delivery efficiency and delay. The results show the robust behavior of the proposed scheme achieving the best efficiency and delay performance for a wide range of scenarios. Furthermore, CRoS-NDN results in low use of processing time and memory for a growing number of prefixes.

scholarly journals DeepFogSim: A Toolbox for Execution and Performance Evaluation of the Inference Phase of Conditional Deep Neural Networks with Early Exits Atop Distributed Fog Platforms

2021 ◽  
Vol 11 (1) ◽  
pp. 377
Author(s):  
Michele Scarpiniti ◽  
Enzo Baccarelli ◽  
Alireza Momenzadeh ◽  
Sima Sarv Ahrabi
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Future Internet ◽  
Operating Conditions ◽  
Graphic User Interface ◽  
Energy Aware ◽  
Internet Applications ◽  
The Real ◽  
Delay Performance ◽  
Hard Constraints

The recent introduction of the so-called Conditional Neural Networks (CDNNs) with multiple early exits, executed atop virtualized multi-tier Fog platforms, makes feasible the real-time and energy-efficient execution of analytics required by future Internet applications. However, until now, toolkits for the evaluation of energy-vs.-delay performance of the inference phase of CDNNs executed on such platforms, have not been available. Motivated by these considerations, in this contribution, we present DeepFogSim. It is a MATLAB-supported software toolbox aiming at testing the performance of virtualized technological platforms for the real-time distributed execution of the inference phase of CDNNs with early exits under IoT realms. The main peculiar features of the proposed DeepFogSim toolbox are that: (i) it allows the joint dynamic energy-aware optimization of the Fog-hosted computing-networking resources under hard constraints on the tolerated inference delays; (ii) it allows the repeatable and customizable simulation of the resulting energy-delay performance of the overall Fog execution platform; (iii) it allows the dynamic tracking of the performed resource allocation under time-varying operating conditions and/or failure events; and (iv) it is equipped with a user-friendly Graphic User Interface (GUI) that supports a number of graphic formats for data rendering. Some numerical results give evidence for about the actual capabilities of the proposed DeepFogSim toolbox.

AND-OR-XOR NETWORK SYNTHESIS WITH AREA-POWER TRADE-OFF

2011 ◽  
Vol 20 (06) ◽  
pp. 1019-1035 ◽  
Author(s):  
SAMBHU NATH PRADHAN ◽  
M. TILAK KUMAR ◽  
SANTANU CHATTOPDHYAY
Keyword(s):  
Boolean Function ◽  
Solution Space ◽  
Leakage Power ◽  
Total Power ◽  
Synthesis Process ◽  
Network Synthesis ◽  
Trade Off ◽  
Delay Performance ◽  
Trade Offs ◽  
Power Trade

In this paper, a heuristic based on genetic algorithm to realize multi-output Boolean function as three-level AND-OR-XOR network performing area power trade-off is presented. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR networks synthesis. The synthesis process, without changing the delay performance results in lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power, and leakage power of the resulting circuit.

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