Development and implementation of a Network Processor Architecture in reconfigurable logic (FPGA)

2010 8th Workshop on Intelligent Solutions in Embedded Systems ◽

10.1109/wises.2010.5548436 ◽

2010 ◽

Cited By ~ 1

Author(s):

Constantinos Stefanatos ◽

Ioannis Papaefstathiou ◽

Charalampos Manifavas

Keyword(s):

Network Processor ◽

Processor Architecture ◽

Reconfigurable Logic

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Agere Systems–Communications Optimized PayloadPlus Network Processor Architecture

Network Processor Design ◽

10.1016/b978-155860875-7.50028-4 ◽

2003 ◽

pp. 219-233

Author(s):

Bill Klein ◽

Juan Garza

Keyword(s):

Network Processor ◽

Processor Architecture

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FlexPath NP - A network processor architecture with flexible processing paths

2008 International Symposium on System-on-Chip ◽

10.1109/issoc.2008.4694869 ◽

2008 ◽

Cited By ~ 6

Author(s):

Michael Meitinger ◽

Rainer Ohlendorf ◽

Thomas Wild ◽

Andreas Herkersdorf

Keyword(s):

Network Processor ◽

Processor Architecture

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A folded pipeline network processor architecture for 100 Gbit/s networks

Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '10 ◽

10.1145/1872007.1872010 ◽

2010 ◽

Cited By ~ 6

Author(s):

Kimon Karras ◽

Thomas Wild ◽

Andreas Herkersdorf

Keyword(s):

Network Processor ◽

Processor Architecture ◽

Pipeline Network

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Network processor architecture for IPSec

The 6th International Conference on Advanced Communication Technology, 2004. ◽

10.1109/icact.2004.1292915 ◽

2004 ◽

Cited By ~ 1

Author(s):

Minho Han ◽

Jeongnyeo Kim ◽

Seungwon Sohn

Keyword(s):

Network Processor ◽

Processor Architecture

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A new network processor architecture for high-speed communications

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822361 ◽

2003 ◽

Cited By ~ 5

Author(s):

Xiaoning Nie ◽

L. Gazsi ◽

F. Engel ◽

G. Fettweis

Keyword(s):

High Speed ◽

Network Processor ◽

Processor Architecture

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Network processor architecture for flexible buffer management in very high speed line interfaces

10.1117/12.434375 ◽

2001 ◽

Author(s):

Shimonishi Hideyuki ◽

Murase Tutomu

Keyword(s):

High Speed ◽

Buffer Management ◽

Network Processor ◽

Processor Architecture ◽

Very High

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A network processor architecture for flexible QoS control in very high-speed line interfaces

2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552) ◽

10.1109/hpsr.2001.923669 ◽

2002 ◽

Cited By ~ 10

Author(s):

H. Shimonishi ◽

T. Murase

Keyword(s):

High Speed ◽

Network Processor ◽

Processor Architecture ◽

Qos Control ◽

Very High

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Network processor architecture with flow-based dynamic bandwidth control for efficient QoS provisioning

Peer-to-Peer Networking and Applications ◽

10.1007/s12083-013-0227-1 ◽

2013 ◽

Vol 8 (4) ◽

pp. 704-715

Author(s):

Jongsu Park ◽

Yong-Surk Lee

Keyword(s):

Network Processor ◽

Processor Architecture ◽

Qos Provisioning ◽

Bandwidth Control ◽

Dynamic Bandwidth

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DynaNP - A Coarse-grain Dataflow Network Processor Architecture with Dynamic Configurable Processing Path

Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2007) ◽

10.1109/snpd.2007.384 ◽

2007 ◽

Author(s):

Tao Li ◽

Xiao-ming Zhang ◽

Zhi-gang Sun

Keyword(s):

Network Processor ◽

Coarse Grain ◽

Processor Architecture

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Processing and scheduling components in an innovative network processor architecture

16th International Conference on VLSI Design, 2003. Proceedings. ◽

10.1109/icvd.2003.1183136 ◽

2003 ◽

Cited By ~ 5

Author(s):

K. Vlachos ◽

N. Nikolaou ◽

T. Orphanoudakis ◽

S. Perissakis ◽

D. Pnevmatikatos ◽

...

Keyword(s):

Network Processor ◽

Processor Architecture

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