Reducing test application time for built-in-self-test test pattern generators

2002 ◽  
Author(s):  
I. Hamzaoglu ◽  
J.H. Patel
Keyword(s):  
Test Pattern ◽  
Application Time ◽  
Test Application Time ◽  
Test Application ◽  
Self Test ◽  
Built In Self Test ◽  
Pattern Generators

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

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