ABSTRACTUsing CMOS, poly-Si gate, single-level metal, gate-array chips, techniques have been developed to reconfigure the interconnect metallization on individual circuits without degradation of device or circuit performance. These techniques involve a laser-assisted capillary wet-etch process for highly selective removal of Al-alloy interconnects and laser CVD of doped poly-Si links. This technique may be useful for prototyping, testing and optimization of gate-array and standard-cell designs and layouts.