High speed sub-halfmicron flash memory technology with simple stacked gate structure cell

2002 ◽  
Author(s):  
S. Mori ◽  
E. Sakagami ◽  
Y. Yamaguchi ◽  
E. Kamiya ◽  
M. Tanimoto ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Gate Structure

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

2009 ◽  
Vol E92-C (5) ◽  
pp. 659-663 ◽  
Author(s):  
Doo-Hyun KIM ◽  
Il Han PARK ◽  
Seongjae CHO ◽  
Jong Duk LEE ◽  
Hyungcheol SHIN ◽  
...  
Keyword(s):  
Flash Memory ◽  
Double Gate ◽  
Gate Structure ◽  
Retention Characteristics

Hierarchical Request-Size-Aware Flash Translation Layer Based on Page-Level Mapping

2019 ◽  
Vol 28 (07) ◽  
pp. 1950117 ◽  
Author(s):  
Dong Bin Yeo ◽  
Joon-Yong Paik ◽  
Tae-Sun Chung
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Garbage Collection ◽  
Good Alternative ◽  
Performance Degradation ◽  
Digital Data ◽  
Mass Storage ◽  
Special Area ◽  
Flash Translation Layer ◽  
Request Size

Owing to the increasing Internet population, there has been an explosion in the amount of digital data generated and also an increase in data complexity. This trend is called big data paradigm. As the Internet of Things (IoT) takes center stage, the growth of data will continue to increase. Therefore, the demand for mass storage devices that have high access speed is increasing. Industry has been paying attention to flash memories that can process large amounts of data at high speed. It will be a good alternative for storing and processing ever-increasing amounts of data because of low power consumption, high shock resistance, portability and fast access speed. However, the write speed is about 10–20 times slower than the read speed in flash memory. In addition, write operations are not allowed to be performed with in-place updates. Garbage collection mechanism is proposed in order to solve the problem incurred by the not-in-place update property of write operations. However, garbage collection mechanism unavoidably causes overhead of additional internal operations, which leads to performance degradation. In this paper, to prevent performance degradation caused by garbage collection, we propose a request-size-aware flash translation layer (RSaFTL) and a hierarchical request-size-aware flash translation layer (HiRSaFTL). They are designed based on page-level address translation. In RSaFTL and HiRSaFTL, page-sized data with high temporal locality cluster into a special area called active blocks by exploiting the property of realistic traces. As a result of the experiments, RSaFTL and HiRSaFTL reduce the number of pages migrated during garbage collections by up to 17.9% and 21.3%, respectively, compared with pure page-level flash transition layer.

A novel bit-line direct-sense circuit that uses a feedback system for high-speed Flash memory

2006 ◽  
Vol 89 (8) ◽  
pp. 1-8
Author(s):  
Takuya Kadowaki ◽  
Hiroki Nakamura ◽  
Hiroshi Sakuraba ◽  
Fujio Masuoka
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Feedback System

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

The Application of Flash Memory in Computerized Jacquard Controller

2012 ◽  
Vol 182-183 ◽  
pp. 706-710 ◽  
Author(s):  
Cheng Jun Zhang ◽  
Xiao Yan Zuo ◽  
Chi Zhang ◽  
Xiao Guang Wu
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Data Transfer ◽  
Data Access ◽  
Management Procedures ◽  
File Structure ◽  
High Speed Data

Through analyzing the pattern data of computerized jacquard knitting wrap machine, comparing the current storages structure and type, this paper introduces a method for Flash file structure of jacquard data. The method takes advantage of ARM chip to achieve the operations for access and modification of Flash, designing a management procedures of jacquard data access from the perspective of increasing the Flash life. The management procedures not only complete read and write operations, but also meet the requirement of jacquard high-speed data transfer.

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