Conductive channel in ONO formed by controlled dielectric breakdown

2003 ◽  
Author(s):  
S. Chiang ◽  
R. Wang ◽  
T. Speers ◽  
J. McCollum ◽  
E. Hamdy ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Conductive Channel

Effects of Electrical Discharges in Low Pressure Gases on the Morphology of Polyethylene Crystals

1974 ◽  
Vol 32 ◽  
pp. 544-545
Author(s):  
L.H. Bolz ◽  
D.H. Reneker
Keyword(s):  
Power Distribution ◽  
Electrical Discharge ◽  
Dielectric Breakdown ◽  
Ionic Species ◽  
Low Pressure ◽  
Polymer Surfaces ◽  
Electrical Discharges ◽  
Adhesive Bonds ◽  
Power Distribution Lines ◽  
Modification Of The Surface

The attack, on the surface of a polymer, by the atomic, molecular and ionic species that are created in a low pressure electrical discharge in a gas is interesting because: 1) significant interior morphological features may be revealed, 2) dielectric breakdown of polymeric insulation on high voltage power distribution lines involves the attack on the polymer of such species created in a corona discharge, 3) adhesive bonds formed between polymer surfaces subjected to such SDecies are much stronger than bonds between untreated surfaces, 4) the chemical modification of the surface creates a reactive surface to which a thin layer of another polymer may be bonded by glow discharge polymerization.

Dielectric Breakdown Properties of Poly-Lactic Acid with Spherulites Growth

2014 ◽  
Vol 134 (4) ◽  
pp. 237-242
Author(s):  
Naru Matsugasaki ◽  
Katsuyoshi Shinyama ◽  
Shigetaka Fujita
Keyword(s):  
Lactic Acid ◽  
Dielectric Breakdown ◽  
Poly Lactic Acid

Dielectric Breakdown of Transformer Insulation Materials Under Cryogenic and Room Temperatures

2008 ◽  
Author(s):  
Horatio Rodrigo ◽  
Wolfgang Baumgartinger ◽  
Aniket Ingrole ◽  
Z (Richard) Liang ◽  
Danny George. Crook ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Insulation Materials ◽  
Transformer Insulation

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

A Novel Integrated Reliability Test System for BEOL TDDB Study

2012 ◽  
Author(s):  
Jifeng Chen ◽  
Peilin Song ◽  
Thomas M. Shaw ◽  
Franco Stellari ◽  
Lynne Gignac ◽  
...  
Keyword(s):  
Preliminary Analysis ◽  
Dielectric Breakdown ◽  
Test System ◽  
Accurate Information ◽  
Reliability Test ◽  
Electrical Measurements ◽  
Time Dependent Dielectric Breakdown ◽  
Microscopy Images ◽  
Insight Into

Abstract In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.

Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

1998 ◽  
Author(s):  
H. Lorenz ◽  
C. Engel
Keyword(s):  
Focused Ion Beam ◽  
Cell Function ◽  
Dielectric Breakdown ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Floating Gate ◽  
Leakage Path ◽  
Contrast Technique ◽  
Voltage Contrast

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

Dielectric Breakdown in Printed Circuit Boards at Elevated Temperatures

1996 ◽  
Author(s):  
P. Singh ◽  
G.T. Galyon ◽  
J. Obrzut ◽  
W.A. Alpaugh
Keyword(s):  
Experimental Data ◽  
Thermal Degradation ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Elevated Temperatures ◽  
Dielectric Breakdown ◽  
Circuit Board ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Data Matching

Abstract A time delayed dielectric breakdown in printed circuit boards, operating at temperatures below the epoxy resin insulation thermo-electrical limits, is reported. The safe temperature-voltage operating regime was estimated and related to the glass-rubber transition (To) of printed circuit board dielectric. The TG was measured using DSC and compared with that determined from electrical conductivity of the laminate in the glassy and rubbery state. A failure model was developed and fitted to the experimental data matching a localized thermal degradation of the dielectric and time dependency. The model is based on localized heating of an insulation resistance defect that under certain voltage bias can exceed the TG, thus, initiating thermal degradation of the resin. The model agrees well with the experimental data and indicates that the failure rate and truncation time beyond which the probability of failure becomes insignificant, decreases with increasing glass-rubber transition temperature.

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