Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers

2018 ◽  
Author(s):  
Qadeer A. Khan ◽  
Seong-Joong Kim ◽  
Pavan Kumar Hanumolu
Keyword(s):  
High Speed ◽  
Digital Controllers ◽  
Fully Integrated ◽  
High Speed Switching

High-speed digital controllers using an 8 bit microprocessor

1985 ◽  
Vol 4 (5-6) ◽  
pp. 109 ◽  
Author(s):  
R.M. Goodall ◽  
D.S. Brown
Keyword(s):  
High Speed ◽  
Digital Controllers

High-Speed Switching Method of MOSFETs Using Switching Assist Auxiliary Circuit

2013 ◽  
Vol 133 (12) ◽  
pp. 1186-1192
Author(s):  
Toshihiko Noguchi ◽  
Tomohiro Mizuno ◽  
Munehiro Murata
Keyword(s):  
High Speed ◽  
Switching Method ◽  
High Speed Switching ◽  
Auxiliary Circuit

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

High‐Speed Switching in Metal Bridges

1970 ◽  
Vol 41 (6) ◽  
pp. 2745-2747 ◽  
Author(s):  
R. I. Gayley ◽  
J. D. Langan ◽  
K. Kim
Keyword(s):  
High Speed ◽  
High Speed Switching

scholarly journals In-Plane Monolithic Integration of Scaled III-V Photonic Devices

2021 ◽  
Vol 11 (4) ◽  
pp. 1887
Author(s):  
Markus Scherrer ◽  
Noelia Vico Triviño ◽  
Svenja Mauthe ◽  
Preksha Tiwari ◽  
Heinz Schmid ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Photonic Devices ◽  
Monolithic Integration ◽  
Light Emitters ◽  
Fully Integrated ◽  
Large Lattice ◽  
Hybrid Iii ◽  
Gain Material

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

High-Speed Switching in Fibres with Electrodes

2007 ◽  
Author(s):  
L-E. Nilsson ◽  
Z. Yu ◽  
O. Tarasenko ◽  
H. Knape ◽  
P-Y. Fonjallaz ◽  
...  
Keyword(s):  
High Speed ◽  
High Speed Switching
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