Formal Verification of Power Management Logic with Mixed-Signal Domains

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid.2017.43 ◽

2017 ◽

Cited By ~ 2

Author(s):

Sudipa Mandal ◽

Antonio Bruto Da Costa ◽

Aritra Hazra ◽

Pallab Dasgupta ◽

Bhushan Naware ◽

...

Keyword(s):

Formal Verification ◽

Power Management ◽

Mixed Signal

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Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces

Journal of Electronic Testing ◽

10.1007/s10836-013-5407-7 ◽

2013 ◽

Vol 29 (5) ◽

pp. 715-740 ◽

Cited By ~ 1

Author(s):

Kusum Lata ◽

Subir K. Roy

Keyword(s):

Formal Verification ◽

Circuit Simulation ◽

Mixed Signal

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Formal Verification of Analog and Mixed Signal Designs: Survey and Comparison

2006 IEEE North-East Workshop on Circuits and Systems ◽

10.1109/newcas.2006.250926 ◽

2006 ◽

Cited By ~ 8

Author(s):

Mohamed Zaki ◽

Sofiene Tahar ◽

Guy Bois

Keyword(s):

Formal Verification ◽

Mixed Signal

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Assertions for Protecting Mixed-Signal Latency Contracts in Power Management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2020.3002481 ◽

2020 ◽

Vol 28 (8) ◽

pp. 1745-1756

Author(s):

Sudipa Mandal ◽

Pallab Dasgupta ◽

Aritra Hazra ◽

Chunduri Rama Mohan

Keyword(s):

Power Management ◽

Mixed Signal

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Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid.2018.34 ◽

2018 ◽

Author(s):

Sudipa Mandal ◽

Aritra Hazra ◽

Pallab Dasgupta ◽

Rama Mohan Chunduri

Keyword(s):

Formal Methods ◽

Power Management ◽

Mixed Signal ◽

Coverage Analysis

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Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

10.1109/asqed.2009.5206276 ◽

2009 ◽

Cited By ~ 6

Author(s):

Kusum Lata ◽

Subir K. Roy ◽

H.S. Jamadagni

Keyword(s):

Formal Verification ◽

Circuit Simulation ◽

Mixed Signal

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Formal verification of mixed-signal designs using extended affine arithmetic

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) ◽

10.1109/prime.2016.7519482 ◽

2016 ◽

Cited By ~ 4

Author(s):

Carna Radojicic ◽

Christoph Grimm

Keyword(s):

Formal Verification ◽

Affine Arithmetic ◽

Mixed Signal

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On-chip low-power circuit techniques for power management regulators in mixed-signal integrated circuits

10.14711/thesis-b1180241 ◽

2012 ◽

Author(s):

Ngai Yeung Ho

Keyword(s):

Integrated Circuits ◽

Low Power ◽

Power Management ◽

Power Circuit ◽

Mixed Signal ◽

Circuit Techniques ◽

On Chip

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Formal verification of synthesized mixed signal designs using *BMDs

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design ◽

10.1109/icvd.2000.812589 ◽

2002 ◽

Author(s):

A. Ghosh ◽

R. Vemuri

Keyword(s):

Formal Verification ◽

Mixed Signal

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Multicore power management: Ensuring robustness via early-stage formal verification

2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design ◽

10.1109/memcod.2009.5185383 ◽

2009 ◽

Cited By ~ 18

Author(s):

Anita Lungu ◽

Pradip Bose ◽

Daniel J. Sorin ◽

Steven German ◽

Geert Janssen

Keyword(s):

Formal Verification ◽

Power Management ◽

Early Stage

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Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

Theoretical Computer Science ◽

10.1016/j.tcs.2008.03.032 ◽

2008 ◽

Vol 404 (3) ◽

pp. 293-307

Author(s):

Jens Schönherr ◽

Martin Freibothe ◽

Bernd Straube ◽

Jörg Bormann

Keyword(s):

Steady State ◽

Formal Verification ◽

State Behavior ◽

Mixed Signal ◽

Mixed Signal Circuits ◽

Steady State Behavior

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