System Efficiency Improvement Technique for Automotive Power Management IC Using Maximum Load Current Selector Circuit

2016 ◽  
Author(s):  
Krishna Kanth Gowri Avalur ◽  
Syed Azeemuddin
Keyword(s):  
Power Management ◽  
Maximum Load ◽  
Efficiency Improvement ◽  
System Efficiency ◽  
Load Current ◽  
Power Management Ic

CFD-Analysis of Coverplate Receiver Flow

1996 ◽  
Author(s):  
Oliver Popp ◽  
Horst Zimmermann ◽  
J. Kutz
Keyword(s):  
Turbine Rotor ◽  
Geometrical Parameters ◽  
Receiver Design ◽  
Cfd Analysis ◽  
Efficiency Improvement ◽  
System Efficiency ◽  
Cfd Simulations ◽  
Air Supply ◽  
Cooling Air ◽  
Contour Design

The flow field in a preswirled cooling air supply to a turbine rotor has been investigated by means of CFD-simulations. Coefficients for system efficiency are derived. The influences of various geometrical parameters for different configurations have been correlated with the help of appropriate coefficients. For some of the most important geometrical parameters of the coverplate receiver design recommendations have been found. For the preswirl nozzles the potential of efficiency improvement by contour design is highlighted.

A Three-Stage Coarse-Fine-Tuning Analog-Assisted Digital LDO

2020 ◽  
pp. 2150047
Author(s):  
Lianxi Liu ◽  
Yiwei Chen ◽  
Xufeng Liao ◽  
Junchao Mu ◽  
Yintang Yang
Keyword(s):  
Output Voltage ◽  
Maximum Load ◽  
Input Voltage ◽  
Fine Tuning ◽  
Cmos Process ◽  
Load Current ◽  
Input Range ◽  
Low Dropout Regulator ◽  
Layout Area ◽  
Two Stages

This paper proposes a three-stage coarse-fine-tuning analog-assisted digital low dropout regulator (AAD-LDO) without digital ripple. The digital regulation consists of two stages, which break the accuracy-speed-power trade-off. To further improve transient response, a step-variable counter used in the first stage is designed, which makes sure that the output current can track the load current rapidly. The ripple caused by the digital regulation disappears due to the existence of the analog-assistant stage (in the proposed AAD-LDO). As a result, the AAD-LDO achieves the output voltage with high accuracy. Designed in a 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed AAD-LDO has a layout area of 0.133[Formula: see text]mm. For the input range of 1.2–1.8[Formula: see text]V, the output voltage is 1[Formula: see text]V. The maximum load current is 10[Formula: see text]mA at the input voltage of 1.2[Formula: see text]V. The linear regulation and load regulation are 0.061[Formula: see text]mV/V and 0.0082[Formula: see text]mV/mA, respectively. The over/undershoot is suppressed effectively for a 9.5[Formula: see text]mA load step. The peak current efficiency is 99.78%.

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