A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits

2015 ◽  
Author(s):  
Sameer Pawanekar ◽  
Gaurav Trivedi ◽  
Kalpesh Kapoor
Keyword(s):  
Optimization Method ◽  
Vlsi Circuits ◽  
Standard Cell ◽  
Cell Placement

scholarly journals An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement

VLSI Design ◽  
1999 ◽  
Vol 10 (2) ◽  
pp. 169-176
Author(s):  
Jin-Tai Yan
Keyword(s):  
Linear Programming ◽  
Vlsi Circuits ◽  
Total Cell ◽  
Cell Area ◽  
Standard Cell ◽  
Standard Cells ◽  
A Cell ◽  
Cell Placement ◽  
Layout Area ◽  
Search Approach

It is well known that standard cells have been widely used to implement VLSI circuits in the automation of physical design. Since one major aim of a cell-based design is to minimize total layout area in a standard cell placement, the number of feedthrough cells will be minimized to reduce total cell area in a standard cell placement. In this paper, first, we model a partitioning-based row assignment (PRA) problem to minimize the number of feedthrough cells in a standard cell placement. Furthermore, an integer linear programming (ILP) approach is proposed to solve the PRA problem in a standard cell placement. Finally, the ILP approach has been implemented and two standard-cell netlists, Primary 1 and Primary 2, have been tested by the proposed approach, Bose's approach [4] and an exhaustive search approach, respectively. The experimental results show that the ILP approach obtains fewer feedthrough cells than Bose's approach in a partitioning-based standard cell placement.

Modern Standard-cell Placement Techniques

2001 ◽  
pp. 45-87
Author(s):  
Xiaojian Yang ◽  
Elaheh Bozorgzadeh ◽  
Majid Sarrafzadeh ◽  
Maogang Wang
Keyword(s):  
Standard Cell ◽  
Cell Placement ◽  
Modern Standard

scholarly journals Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Technologies ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 3
Author(s):  
Panagiotis Oikonomou ◽  
Antonios Dadaliaris ◽  
Kostas Kolomvatsos ◽  
Thanasis Loukopoulos ◽  
Athanasios Kakarountas ◽  
...  
Keyword(s):  
Target Function ◽  
Problem Formulation ◽  
Search Space ◽  
Standard Cell ◽  
Chip Area ◽  
Time Performance ◽  
Trade Offs ◽  
Cell Placement ◽  
Placement Algorithm ◽  
Algorithmic Approaches

In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

Design of Optimal CMOS Analog Amplifier Circuits Using a Hybrid Evolutionary Optimization Technique

2017 ◽  
Vol 27 (02) ◽  
pp. 1850029 ◽  
Author(s):  
Bishnu Prasad De ◽  
Kanchan Baran Maji ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Power Dissipation ◽  
Optimization Problems ◽  
Optimization Technique ◽  
Optimization Method ◽  
Vlsi Circuits ◽  
Optimal Designs ◽  
Efficient Design ◽  
Mos Transistors ◽  
Evolutionary Technique ◽  
Random Particle

This paper proposes an efficient design technique for two commonly used VLSI circuits, namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage operational amplifier. The hybrid evolutionary method utilized for these optimal designs is random particle swarm optimization with differential evolution (RPSODE). Random PSO utilizes the weighted particles for monitoring the search directions. DE is a robust evolutionary technique. It has demonstrated an exclusive performance for the optimization problems which are continuous and global but suffers from the uncertainty issues. PSO is a robust optimization method but suffers from sub-optimality problem. This paper effectively hybridizes the random PSO and DE to remove the limitations related to both the techniques individually. In this paper, RPSODE is employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained from RPSODE technique are validated in SPICE environment. SPICE-based simulation results justify that RPSODE is a much better technique than other formerly reported methods for the designs of the above mentioned circuits in terms of MOS area, gain, power dissipation, etc.

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