A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes

2007 ◽  
Author(s):  
Kiran Gunnam ◽  
Gwan Choi ◽  
Mark Yeary
Keyword(s):  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Layered Decoding ◽  
Array Ldpc Codes

Layered Decoding of Non-Layered LDPC Codes

2006 ◽  
Author(s):  
M. Rovini ◽  
F. Rossi ◽  
P. Ciao ◽  
N. L'Insalata ◽  
L. Fanucci
Keyword(s):  
Ldpc Codes ◽  
Layered Decoding

scholarly journals A Parallel Layered Decoding Algorithm for Non-layered LDPC Codes

2010 ◽  
Vol 32 (8) ◽  
pp. 1956-1960
Author(s):  
Kun Guo ◽  
Yong Hei ◽  
Yu-mei Zhou ◽  
Shu-shan Qiao
Keyword(s):  
Ldpc Codes ◽  
Decoding Algorithm ◽  
Layered Decoding

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

On the Burst Erasure Efficiency of Array LDPC Codes

2015 ◽  
Vol 83 (2) ◽  
pp. 1313-1329
Author(s):  
Mohammad Hesam Tadayon ◽  
Asieh Abolpour Mofrad ◽  
Zahra Ferdosi
Keyword(s):  
Ldpc Codes ◽  
Array Ldpc Codes ◽  
Burst Erasure

A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA

2013 ◽  
Vol 61 (11) ◽  
pp. 2940-2951 ◽  
Author(s):  
Yeong-Luh Ueng ◽  
Kuo-Hsuan Liao ◽  
Hsueh-Chih Chou ◽  
Chung-Jay Yang
Keyword(s):  
High Throughput ◽  
Ldpc Codes ◽  
Layered Decoding
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