scholarly journals MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

2007 ◽  
Author(s):  
T.S. Rajesh Kumar ◽  
C.P. Ravikumar ◽  
R. Govindarajan
Keyword(s):  
Embedded Systems ◽  
Memory Architecture ◽  
Multi Objective ◽  
Architecture Exploration ◽  
Systems On Chip ◽  
On Chip

scholarly journals Component reuse methodology for multi-clock Data-Flow parallel embedded Systems

2014 ◽  
Vol Volume 18, 2014 ◽  
Author(s):  
Anne Marie Chana ◽  
Patrice Quinton ◽  
Steven Derrien
Keyword(s):  
Embedded Systems ◽  
Data Flow ◽  
Multidimensional Data ◽  
Systems On Chip ◽  
Reuse Methodology ◽  
Scheduling Method ◽  
On Chip ◽  
Synchronous Data Flow ◽  
Relationship Of ◽  
Flexible Component

International audience The growing complexity of new chips and the time-to-market constraints require fundamental changes in the way systems are designed. Systems on Chip (SoC) based on reused components have become an absolute necessity to embedded systems companies that want to remain competitive. However, the design of a SoC is extremely complex because it encompasses a range of difficult problems in hardware and software design. This paper focuses on the design of parallel and multi-frequency applications using flexible components. Flexible parallel components are assembled using a scheduling method which combines the synchronous data-flow principle of balance equations and the polyhedral scheduling technique. Our approach allows a flexible component to be modelled and a full system to be assembled and synthesized with automatically generated wrappers. The work presented here is an extension of previous work. We illustrate our method on a simplified WCDMA system. We discuss the relationship of this approach with multi-clock architecture, latency-insensitive design, multidimensional data-flow systems and stream programming

Sign in / Sign up

Export Citation Format

Share Document