Multi-level parallelism analysis of face detection on a shared memory multi-core system

2011 ◽  
Author(s):  
Chih-Hsuan Chiang ◽  
Chih-Heng Kao ◽  
Guan-Ru Li ◽  
Bo-Cheng Charles Lai
Keyword(s):  
Shared Memory ◽  
Face Detection ◽  
Core System ◽  
Multi Level ◽  
Level Parallelism

scholarly journals The design and evaluation of hierarchical multi-level parallelisms for H.264 encoder on multi-core architecture

2010 ◽  
Vol 7 (1) ◽  
pp. 189-200 ◽  
Author(s):  
Haitao Wei ◽  
Yu Junqing ◽  
Li Jiang
Keyword(s):  
Video Coding ◽  
Experimental Results ◽  
Bit Rate ◽  
Low Bit Rate ◽  
Good Compromise ◽  
Multi Level ◽  
Level Parallelism ◽  
Data Level ◽  
Intel Xeon

As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates four level parallelisms - frame-level, slice-level, macroblock-level and data-level into one implementation. Each level parallelism is designed in a hierarchical parallel framework and mapped onto the multi-cores and SIMD units on multi-core architecture. According to the analysis of coding performance on each level parallelism, we propose a method to combine different parallel levels to attain a good compromise between high speedup and low bit-rate. The experimental results show that for CIF format video, our method achieves the speedup of 33.57x-42.3x with 1.04x-1.08x bit-rate increasing on 8-core Intel Xeon processor with SIMD Technology.

Exploring Multi-level Parallelism in Cellular Automata Networks

2000 ◽  
pp. 336-343 ◽  
Author(s):  
Claudia Roberta Calidonna ◽  
Claudia Di Napoli ◽  
Maurizio Giordano ◽  
Mario Mango Furnari
Keyword(s):  
Cellular Automata ◽  
Automata Networks ◽  
Multi Level ◽  
Level Parallelism

scholarly journals Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 118707-118724 ◽  
Author(s):  
Leonardo Suriano ◽  
Andres Otero ◽  
Alfonso Rodriguez ◽  
Manuel Sanchez-Renedo ◽  
Eduardo De La Torre
Keyword(s):  
Inverse Kinematics ◽  
Multi Level ◽  
Run Time ◽  
Level Parallelism

scholarly journals FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

2018 ◽  
Vol 7 (2.16) ◽  
pp. 57
Author(s):  
G Prasad Acharya ◽  
M Asha Rani
Keyword(s):  
Computer Aided Design ◽  
Processing System ◽  
System On Chip ◽  
Core System ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Aided Design ◽  
Level Parallelism

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.  

scholarly journals Exploiting Multi-Level Parallelism for Stitching Very Large Microscopy Images

2019 ◽  
Vol 13 ◽  
Author(s):  
Alessandro Bria ◽  
Massimo Bernaschi ◽  
Massimiliano Guarrasi ◽  
Giulio Iannello
Keyword(s):  
Multi Level ◽  
Level Parallelism ◽  
Microscopy Images

The Design and Implementation of a Heterogeneous Multi-Core Security Chip Architecture Based on Shared Memory System

2014 ◽  
Vol 668-669 ◽  
pp. 1314-1318
Author(s):  
Lei Zhang ◽  
Ren Ping Dong ◽  
Chang Zhang ◽  
Ya Ping Yu
Keyword(s):  
Low Power ◽  
Computer Architecture ◽  
Shared Memory ◽  
High Performance ◽  
Stream Cipher ◽  
Ic Card ◽  
Task Partitioning ◽  
Core System ◽  
Design And Implementation ◽  
Encryption And Decryption

With the existence of traditional SOC chip, the encryption and decryption speed and low power cannot meet the computing needs of the modern diversity, then we present a heterogeneous multi-core system which designed based on shared memory on the Xilinx Virtex-5 platform. This paper is in-depth research about heterogeneous multi-core password architecture, static task partitioning, scheduling strategy and the communication mechanism between cores. The three cores systems are designed and builded based on shared memory to realize ZUC algorithm which generates a stream cipher on virtex-5 platform. The three microblaze cores are responsible for inter-core communication, the implementation of ZUC algorithm and articulating IC card to read keys. Through the design of three cores system, give full play to the hardware, software and computer architecture parallelism at all levels to improve the performance of the algorithm to achieve high performance green computing.

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