System Redundancy; A Means of Improving Process Variation Yield Degradation in Memory Arrays

2006 ◽  
Author(s):  
Ahmed Eltawil ◽  
Fadi Kurdahi
Keyword(s):  
Process Variation ◽  
Memory Arrays

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

scholarly journals Workload-aware Electromigration Analysis in Emerging Spintronic Memory Arrays

2021 ◽  
pp. 1-1
Author(s):  
Sarath Mohanachandran Nair ◽  
Mahta Mayahinia ◽  
Mehdi B. Tahoori ◽  
Manu Perumkunnil ◽  
Houman Zahedmanesh ◽  
...  
Keyword(s):  
Memory Arrays

Enabling Wavelength-Dependent Adjoint-Based Methods for Process Variation Sensitivity Analysis in Silicon Photonics

2020 ◽  
pp. 1-1
Author(s):  
Zhengxing Zhang ◽  
Sally I. El-Henawy ◽  
Allan Sadun ◽  
Ryan Miller ◽  
Luca Daniel ◽  
...  
Keyword(s):  
Sensitivity Analysis ◽  
Silicon Photonics ◽  
Process Variation

LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN
Keyword(s):  
Supply Voltage ◽  
Process Variation ◽  
Power Saving ◽  
Lookup Table ◽  
Low Leakage ◽  
Fine Grain ◽  
Body Biasing ◽  
Block Level ◽  
Adaptive Body Bias ◽  
Body Bias

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

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