An Area and Power Efficient Radiation Hardened by Design Flip-Flop

2006 ◽  
Vol 53 (6) ◽  
pp. 3392-3399 ◽  
Author(s):  
Jonathan E. Knudsen ◽  
Lawrence T. Clark
Keyword(s):  
Flip Flop ◽  
Power Efficient ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop

2019 ◽  
Vol 18 ◽  
pp. 1089-1096 ◽  
Author(s):  
Abdolah Amirany ◽  
Fahimeh Marvi ◽  
Kian Jafari ◽  
Ramin Rajaei
Keyword(s):  
Flip Flop ◽  
Radiation Hardened

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

2019 ◽  
Vol 29 (08) ◽  
pp. 2050123 ◽  
Author(s):  
Neethu Anna Sabu ◽  
K. Batri
Keyword(s):  
Vlsi Design ◽  
Cmos Technology ◽  
Flip Flop ◽  
Circuit Performance ◽  
Power Efficient ◽  
Transmission Gate ◽  
Double Edge ◽  
Speed Performance ◽  
Layout Area ◽  
Power Delay Product

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).

Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

2020 ◽  
Vol 67 (6) ◽  
pp. 1144-1151
Author(s):  
Ellis W. Richards ◽  
T. D. Loveless ◽  
J. S. Kauppila ◽  
T. D. Haeffner ◽  
W. T. Holman ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Radiation Hardened ◽  
Radiation Hardened By Design
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