scholarly journals A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process

2009 ◽  
Vol 57 (5) ◽  
pp. 1044-1053 ◽  
Author(s):  
Yuan-Wen Hsiao ◽  
Ming-Dou Ker
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Noise Amplifier ◽  
5 Ghz

A 60 GHz balun low-noise amplifier in 28-nm CMOS for millimeter-wave communication

2019 ◽  
Vol 33 (32) ◽  
pp. 1950396 ◽  
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Jun Chen ◽  
Xianbin Xie ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
60 Ghz ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Millimeter Wave Communication ◽  
28 Nm

In this paper, a 60 GHz complementary metal-oxide-semiconductor (CMOS) balun low-noise amplifier (LNA) was implemented for millimeter-wave communication. To improve the gain and noise performance, slow-wave coplanar waveguides (S-CPW) with high quality factor were designed as input, output, and inter-stage matching networks. At the input port, a balun transformer provides additional passive gain while performing the singled-ended to differential conversion. Implemented in a 28-nm CMOS process, simulated results show that the proposed LNA exhibits a simulated linear gain of 16 dB and a noise figure of 5.6 dB at 60 GHz, with a 3-dB gain bandwidth of 5 GHz (58 GHz–63 GHz). The input return loss is better than −25 dB at the central frequency. The simulated input third-order intercept point (IIP3) is −5 dBm. The circuit draws 35 mA from 1 V supply voltage.

scholarly journals The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
Hemad Heidari Jobaneh
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Design System ◽  
Cmos Process ◽  
Ultralow Power ◽  
Noise Amplifier ◽  
5 Ghz

The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

2009 ◽  
Vol 30 (1) ◽  
pp. 015001 ◽  
Author(s):  
Yang Yi ◽  
Gao Zhuo ◽  
Yang Liqiong ◽  
Huang Lingyi ◽  
Hu Weiwu
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Noise Amplifier
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