scholarly journals Duty Cycle Control for Low-Power-Listening MAC Protocols

2010 ◽  
Vol 9 (11) ◽  
pp. 1508-1521 ◽  
Author(s):  
Christophe J. Merlin ◽  
Wendi B. Heinzelman
Keyword(s):  
Low Power ◽  
Duty Cycle ◽  
Mac Protocols ◽  
Low Power Listening

scholarly journals Cross Layer Adaptation of Check Intervals in Low Power Listening MAC Protocols for Lifetime Improvement in Wireless Sensor Networks

Sensors ◽  
2012 ◽  
Vol 12 (8) ◽  
pp. 10511-10535 ◽  
Author(s):  
Soledad Escolar ◽  
Stefano Chessa ◽  
Jesús Carretero ◽  
Maria-Cristina Marinescu
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Mac Protocols ◽  
Wireless Sensor ◽  
Cross Layer ◽  
Low Power Listening

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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